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Computer works (kinda)

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jose.rodriguezlabra
2019-03-13 12:51:44 -04:00
parent 026eb65861
commit 11a1d99e92
64 changed files with 809 additions and 422 deletions
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78
lab2CA.cache/wt/webtalk_pa.xml
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@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Wed Mar 13 11:12:12 2019"> <application name="pa" timeStamp="Wed Mar 13 12:44:53 2019">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="88e779ed22f94d2db93b335d17c75f15" type="ProjectID"/> <property name="ProjectID" value="88e779ed22f94d2db93b335d17c75f15" type="ProjectID"/>
<property name="ProjectIteration" value="12" type="ProjectIteration"/> <property name="ProjectIteration" value="18" type="ProjectIteration"/>
</section> </section>
<section name="PlanAhead Usage" visible="true"> <section name="PlanAhead Usage" visible="true">
<item name="Project Data"> <item name="Project Data">
@@ -18,50 +18,53 @@ This means code written to parse this file will need to be revisited each subseq
</item> </item>
<item name="Java Command Handlers"> <item name="Java Command Handlers">
<property name="CloseProject" value="4" type="JavaHandler"/> <property name="CloseProject" value="4" type="JavaHandler"/>
<property name="FlipToViewTaskRTLAnalysis" value="1" type="JavaHandler"/>
<property name="OpenDesign" value="1" type="JavaHandler"/> <property name="OpenDesign" value="1" type="JavaHandler"/>
<property name="OpenProject" value="3" type="JavaHandler"/> <property name="OpenProject" value="3" type="JavaHandler"/>
<property name="ReloadDesign" value="1" type="JavaHandler"/> <property name="ReloadDesign" value="1" type="JavaHandler"/>
<property name="ReportTimingSummary" value="3" type="JavaHandler"/> <property name="ReportTimingSummary" value="7" type="JavaHandler"/>
<property name="RunImplementation" value="15" type="JavaHandler"/> <property name="RunImplementation" value="22" type="JavaHandler"/>
<property name="RunSchematic" value="13" type="JavaHandler"/> <property name="RunSchematic" value="16" type="JavaHandler"/>
<property name="RunSynthesis" value="18" type="JavaHandler"/> <property name="RunSynthesis" value="18" type="JavaHandler"/>
<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/> <property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
<property name="SetSourceEnabled" value="2" type="JavaHandler"/> <property name="SetSourceEnabled" value="2" type="JavaHandler"/>
<property name="SetTopNode" value="26" type="JavaHandler"/> <property name="SetTopNode" value="27" type="JavaHandler"/>
<property name="ShowView" value="11" type="JavaHandler"/> <property name="ShowView" value="11" type="JavaHandler"/>
<property name="SimulationClose" value="5" type="JavaHandler"/> <property name="SimulationClose" value="5" type="JavaHandler"/>
<property name="SimulationRun" value="74" type="JavaHandler"/> <property name="SimulationRelaunch" value="15" type="JavaHandler"/>
<property name="SimulationRun" value="79" type="JavaHandler"/>
<property name="TclFind" value="4" type="JavaHandler"/> <property name="TclFind" value="4" type="JavaHandler"/>
<property name="ToggleSelectAreaMode" value="2" type="JavaHandler"/> <property name="ToggleSelectAreaMode" value="2" type="JavaHandler"/>
<property name="ToolsSettings" value="1" type="JavaHandler"/> <property name="ToolsSettings" value="1" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="1" type="JavaHandler"/> <property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/> <property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="6" type="JavaHandler"/> <property name="ViewTaskRTLAnalysis" value="6" type="JavaHandler"/>
<property name="WaveformSaveConfiguration" value="1" type="JavaHandler"/>
<property name="ZoomFit" value="6" type="JavaHandler"/> <property name="ZoomFit" value="6" type="JavaHandler"/>
<property name="ZoomOut" value="1" type="JavaHandler"/> <property name="ZoomOut" value="1" type="JavaHandler"/>
</item> </item>
<item name="Gui Handlers"> <item name="Gui Handlers">
<property name="AbstractSearchablePanel_SHOW_SEARCH" value="1" type="GuiHandlerData"/> <property name="AbstractSearchablePanel_SHOW_SEARCH" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="20" type="GuiHandlerData"/> <property name="BaseDialog_CANCEL" value="27" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="88" type="GuiHandlerData"/> <property name="BaseDialog_OK" value="103" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="10" type="GuiHandlerData"/> <property name="BaseDialog_YES" value="16" type="GuiHandlerData"/>
<property name="ClosePlanner_YES" value="1" type="GuiHandlerData"/> <property name="ClosePlanner_YES" value="1" type="GuiHandlerData"/>
<property name="CmdMsgDialog_MESSAGES" value="2" type="GuiHandlerData"/> <property name="CmdMsgDialog_MESSAGES" value="2" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="11" type="GuiHandlerData"/> <property name="CmdMsgDialog_OK" value="11" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/> <property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="224" type="GuiHandlerData"/> <property name="FileSetPanel_FILE_SET_PANEL_TREE" value="244" type="GuiHandlerData"/>
<property name="FloatingTopDialog_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="12" type="GuiHandlerData"/> <property name="FloatingTopDialog_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="12" type="GuiHandlerData"/>
<property name="FloatingTopDialog_SPECIFY_NEW_TOP_MODULE" value="10" type="GuiHandlerData"/> <property name="FloatingTopDialog_SPECIFY_NEW_TOP_MODULE" value="10" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="160" type="GuiHandlerData"/> <property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="185" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/> <property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="27" type="GuiHandlerData"/> <property name="GraphicalView_ZOOM_FIT" value="35" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="40" type="GuiHandlerData"/> <property name="GraphicalView_ZOOM_IN" value="46" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="28" type="GuiHandlerData"/> <property name="GraphicalView_ZOOM_OUT" value="35" type="GuiHandlerData"/>
<property name="HCodeEditor_BLANK_OPERATIONS" value="6" type="GuiHandlerData"/> <property name="HCodeEditor_BLANK_OPERATIONS" value="6" type="GuiHandlerData"/>
<property name="HCodeEditor_CLOSE" value="9" type="GuiHandlerData"/> <property name="HCodeEditor_CLOSE" value="9" type="GuiHandlerData"/>
<property name="HCodeEditor_COMMANDS_TO_FOLD_TEXT" value="3" type="GuiHandlerData"/> <property name="HCodeEditor_COMMANDS_TO_FOLD_TEXT" value="3" type="GuiHandlerData"/>
<property name="HCodeEditor_DIFF_WITH" value="3" type="GuiHandlerData"/> <property name="HCodeEditor_DIFF_WITH" value="3" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="31" type="GuiHandlerData"/> <property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="36" type="GuiHandlerData"/>
<property name="HInputHandler_INDENT_SELECTION" value="1" type="GuiHandlerData"/> <property name="HInputHandler_INDENT_SELECTION" value="1" type="GuiHandlerData"/>
<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="15" type="GuiHandlerData"/> <property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="15" type="GuiHandlerData"/>
<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/> <property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
@@ -71,58 +74,65 @@ This means code written to parse this file will need to be revisited each subseq
<property name="MainMenuMgr_FLOW" value="2" type="GuiHandlerData"/> <property name="MainMenuMgr_FLOW" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="7" type="GuiHandlerData"/> <property name="MainMenuMgr_PROJECT" value="7" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="2" type="GuiHandlerData"/> <property name="MainMenuMgr_WINDOW" value="2" type="GuiHandlerData"/>
<property name="MainToolbarMgr_RUN" value="2" type="GuiHandlerData"/>
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="2" type="GuiHandlerData"/> <property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="2" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="2" type="GuiHandlerData"/> <property name="MsgTreePanel_MESSAGE_SEVERITY" value="2" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="96" type="GuiHandlerData"/> <property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="124" type="GuiHandlerData"/>
<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="5" type="GuiHandlerData"/> <property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="5" type="GuiHandlerData"/>
<property name="MsgView_WARNING_MESSAGES" value="3" type="GuiHandlerData"/> <property name="MsgView_WARNING_MESSAGES" value="3" type="GuiHandlerData"/>
<property name="NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE" value="61" type="GuiHandlerData"/> <property name="NavigableTimingReportTab_TIMING_REPORT_NAVIGATION_TREE" value="102" type="GuiHandlerData"/>
<property name="NetlistTreeView_NETLIST_TREE" value="1" type="GuiHandlerData"/> <property name="NetlistTreeView_NETLIST_TREE" value="1" type="GuiHandlerData"/>
<property name="OpenFileAction_OK" value="1" type="GuiHandlerData"/> <property name="OpenFileAction_OK" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="29" type="GuiHandlerData"/> <property name="PACommandNames_AUTO_UPDATE_HIER" value="30" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="4" type="GuiHandlerData"/> <property name="PACommandNames_CLOSE_PROJECT" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_MESSAGE_WINDOW" value="1" type="GuiHandlerData"/> <property name="PACommandNames_MESSAGE_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/> <property name="PACommandNames_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_RTL_DESIGN" value="1" type="GuiHandlerData"/> <property name="PACommandNames_OPEN_RTL_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RELOAD_RTL_DESIGN" value="1" type="GuiHandlerData"/> <property name="PACommandNames_RELOAD_RTL_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SELECT_AREA" value="2" type="GuiHandlerData"/> <property name="PACommandNames_SELECT_AREA" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_SET_AS_TOP" value="27" type="GuiHandlerData"/> <property name="PACommandNames_SET_AS_TOP" value="28" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="72" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_RELAUNCH" value="16" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="77" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_FUNCTIONAL" value="1" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_FUNCTIONAL" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_TIMING" value="4" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_TIMING" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_SETTINGS" value="1" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_SETTINGS" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_ENABLE" value="1" type="GuiHandlerData"/> <property name="PACommandNames_SRC_ENABLE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_FIT" value="6" type="GuiHandlerData"/> <property name="PACommandNames_ZOOM_FIT" value="6" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_OUT" value="1" type="GuiHandlerData"/> <property name="PACommandNames_ZOOM_OUT" value="1" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="13" type="GuiHandlerData"/> <property name="PAViews_CODE" value="23" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="43" type="GuiHandlerData"/> <property name="PAViews_PATH_TABLE" value="1" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="10" type="GuiHandlerData"/> <property name="PAViews_PROJECT_SUMMARY" value="48" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="12" type="GuiHandlerData"/>
<property name="PathReportTableView_DESCRIPTION" value="2" type="GuiHandlerData"/>
<property name="PowerResultTab_REPORT_NAVIGATION_TREE" value="1" type="GuiHandlerData"/>
<property name="ProgressDialog_BACKGROUND" value="3" type="GuiHandlerData"/> <property name="ProgressDialog_BACKGROUND" value="3" type="GuiHandlerData"/>
<property name="ProgressDialog_CANCEL" value="4" type="GuiHandlerData"/> <property name="ProgressDialog_CANCEL" value="4" type="GuiHandlerData"/>
<property name="ProjectTab_RELOAD" value="12" type="GuiHandlerData"/> <property name="ProjectTab_RELOAD" value="13" type="GuiHandlerData"/>
<property name="RDICommands_COPY" value="2" type="GuiHandlerData"/> <property name="RDICommands_COPY" value="2" type="GuiHandlerData"/>
<property name="RDICommands_REDO" value="1" type="GuiHandlerData"/> <property name="RDICommands_REDO" value="1" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="71" type="GuiHandlerData"/> <property name="RDICommands_SAVE_FILE" value="71" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="379" type="GuiHandlerData"/> <property name="RDIViews_WAVEFORM_VIEWER" value="417" type="GuiHandlerData"/>
<property name="ReportTimingSummaryDialog_REPORT_TIMING_SUMMARY_DIALOG_TABBED" value="12" type="GuiHandlerData"/> <property name="ReportTimingSummaryDialog_REPORT_TIMING_SUMMARY_DIALOG_TABBED" value="14" type="GuiHandlerData"/>
<property name="ReportTimingSummaryDialog_REPORT_UNCONSTRAINED_PATHS" value="2" type="GuiHandlerData"/> <property name="ReportTimingSummaryDialog_REPORT_UNCONSTRAINED_PATHS" value="6" type="GuiHandlerData"/>
<property name="RunGadget_SHOW_ERROR" value="1" type="GuiHandlerData"/> <property name="RunGadget_SHOW_ERROR" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/> <property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="9" type="GuiHandlerData"/> <property name="SaveProjectUtils_SAVE" value="9" type="GuiHandlerData"/>
<property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="12" type="GuiHandlerData"/> <property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="12" type="GuiHandlerData"/>
<property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="12" type="GuiHandlerData"/> <property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="24" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="10" type="GuiHandlerData"/> <property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="46" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="30" type="GuiHandlerData"/> <property name="SrcMenu_IP_HIERARCHY" value="31" type="GuiHandlerData"/>
<property name="StaleMoreAction_OUT_OF_DATE_DETAILS" value="1" type="GuiHandlerData"/> <property name="StaleMoreAction_OUT_OF_DATE_DETAILS" value="1" type="GuiHandlerData"/>
<property name="StaleRunDialog_NO" value="1" type="GuiHandlerData"/> <property name="StaleRunDialog_NO" value="3" type="GuiHandlerData"/>
<property name="StaleRunDialog_YES" value="1" type="GuiHandlerData"/> <property name="StaleRunDialog_YES" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="10" type="GuiHandlerData"/> <property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="10" type="GuiHandlerData"/>
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/> <property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="25" type="GuiHandlerData"/> <property name="TaskBanner_CLOSE" value="29" type="GuiHandlerData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/> <property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/>
<property name="TclFindDialog_RESULT_NAME" value="2" type="GuiHandlerData"/> <property name="TclFindDialog_RESULT_NAME" value="2" type="GuiHandlerData"/>
<property name="TimingDialogUtils_RESULTS_NAME" value="1" type="GuiHandlerData"/> <property name="TimingDialogUtils_RESULTS_NAME" value="1" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="187" type="GuiHandlerData"/> <property name="TimingItemFlatTablePanel_TABLE" value="3" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="215" type="GuiHandlerData"/>
<property name="WaveformView_PREVIOUS_MARKER" value="1" type="GuiHandlerData"/>
</item> </item>
</section> </section>
</application> </application>

11
lab2CA.runs/.jobs/vrs_config_31.xml Normal file
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@@ -0,0 +1,11 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

11
lab2CA.runs/.jobs/vrs_config_32.xml Normal file
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@@ -0,0 +1,11 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

11
lab2CA.runs/.jobs/vrs_config_33.xml Normal file
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@@ -0,0 +1,11 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

11
lab2CA.runs/.jobs/vrs_config_34.xml Normal file
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@@ -0,0 +1,11 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

11
lab2CA.runs/.jobs/vrs_config_35.xml Normal file
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@@ -0,0 +1,11 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

11
lab2CA.runs/.jobs/vrs_config_36.xml Normal file
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@@ -0,0 +1,11 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

265
lab2CA.runs/impl_1/CPU9bits.vdi
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@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit) # Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Mar 13 11:12:42 2019 # Start of session at: Wed Mar 13 12:45:23 2019
# Process ID: 11884 # Process ID: 13848
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1 # Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace # Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits.vdi # Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits.vdi
@@ -16,13 +16,13 @@ Design is defaulting to constrset: constrs_1
INFO: [Project 1-479] Netlist was created with Vivado 2018.3 INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 583.273 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 580.660 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary: INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed. No Unisim elements were transformed.
4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. 4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully link_design completed successfully
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 588.785 ; gain = 334.348 link_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 586.176 ; gain = 331.543
Command: opt_design Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
@@ -33,53 +33,53 @@ INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.165 . Memory (MB): peak = 592.141 ; gain = 3.355 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.153 . Memory (MB): peak = 588.063 ; gain = 1.887
Starting Cache Timing Information Task Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 16212f689 Ending Cache Timing Information Task | Checksum: 157c4d2af
Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1080.938 ; gain = 488.797 Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1112.590 ; gain = 524.527
Starting Logic Optimization Task Starting Logic Optimization Task
Phase 1 Retarget Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s). INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 16212f689 Phase 1 Retarget | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1175.109 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1204.980 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 16212f689 Phase 2 Constant propagation | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1175.109 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1204.980 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep Phase 3 Sweep
Phase 3 Sweep | Checksum: 16212f689 Phase 3 Sweep | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1175.109 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1204.980 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 16212f689 Phase 4 BUFG optimization | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1175.109 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1204.980 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 16212f689 Phase 5 Shift Register Optimization | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.087 . Memory (MB): peak = 1175.109 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.081 . Memory (MB): peak = 1204.980 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 16212f689 Phase 6 Post Processing Netlist | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.087 . Memory (MB): peak = 1175.109 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.082 . Memory (MB): peak = 1204.980 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary Opt_design Change Summary
========================= =========================
@@ -100,32 +100,32 @@ Opt_design Change Summary
Starting Connectivity Check Task Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1175.109 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.980 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 16212f689 Ending Logic Optimization Task | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 1175.109 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 1204.980 ; gain = 0.000
Starting Power Optimization Task Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 16212f689 Ending Power Optimization Task | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1175.109 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1204.980 ; gain = 0.000
Starting Final Cleanup Task Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 16212f689 Ending Final Cleanup Task | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1175.109 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.980 ; gain = 0.000
Starting Netlist Obfuscation Task Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1175.109 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.980 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 16212f689 Ending Netlist Obfuscation Task | Checksum: 157c4d2af
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1175.109 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.980 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation INFO: [Common 17-83] Releasing license: Implementation
20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. 20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully opt_design completed successfully
opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1175.109 ; gain = 586.324 opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1204.980 ; gain = 618.805
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1175.109 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.980 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write. WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated. INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated.
@@ -154,57 +154,127 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of
Phase 1 Placer Initialization Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1195.590 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.980 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9761e0e0 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fb93d5fd
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1195.590 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1204.980 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1195.590 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.980 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 19236f07e Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1beca6fa2
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1226.531 ; gain = 21.551
Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1e494ed1a Phase 1.3 Build Placer Netlist Model | Checksum: 2a829400b
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1226.531 ; gain = 21.551
Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1e494ed1a Phase 1.4 Constrain Clocks/Macros | Checksum: 2a829400b
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1226.531 ; gain = 21.551
Phase 1 Placer Initialization | Checksum: 1e494ed1a Phase 1 Placer Initialization | Checksum: 2a829400b
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1226.531 ; gain = 21.551
Phase 2 Final Placement Cleanup Phase 2 Global Placement
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1204.129 ; gain = 0.000
Phase 2 Final Placement Cleanup | Checksum: 1e494ed1a
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539 Phase 2.1 Floorplanning
INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 2.1 Floorplanning | Checksum: 2a829400b
Ending Placer Task | Checksum: 19236f07e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1204.129 ; gain = 8.539 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1228.102 ; gain = 23.121
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
Phase 2 Global Placement | Checksum: 2105f6932
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1236.750 ; gain = 31.770
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 2105f6932
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1236.750 ; gain = 31.770
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1f49ee005
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1236.750 ; gain = 31.770
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 261f3e987
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1236.750 ; gain = 31.770
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 261f3e987
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1236.750 ; gain = 31.770
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 3 Detail Placement | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1246.945 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19fa94e5e
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
Ending Placer Task | Checksum: 134f94256
Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1246.945 ; gain = 41.965
INFO: [Common 17-83] Releasing license: Implementation INFO: [Common 17-83] Releasing license: Implementation
38 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. 37 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully place_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1204.129 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1246.945 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write. WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database... Writing placer database...
Writing XDEF routing. Writing XDEF routing.
Writing XDEF routing logical nets. Writing XDEF routing logical nets.
Writing XDEF routing special nets. Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.122 . Memory (MB): peak = 1204.129 ; gain = 0.000 Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.131 . Memory (MB): peak = 1246.945 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated. INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file CPU9bits_io_placed.rpt INFO: [runtcl-4] Executing : report_io -file CPU9bits_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.086 . Memory (MB): peak = 1210.254 ; gain = 6.125 report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.085 . Memory (MB): peak = 1246.945 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1210.254 ; gain = 0.000 report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1246.945 ; gain = 0.000
Command: route_design Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
@@ -216,67 +286,66 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in
Starting Routing Task Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: fad50f9e ConstDB: 0 ShapeSum: 9761e0e0 RouteDB: 0 Checksum: PlaceDB: 39656c59 ConstDB: 0 ShapeSum: fb93d5fd RouteDB: 0
Phase 1 Build RT Design Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: ae2d8a92 Phase 1 Build RT Design | Checksum: fe327772
Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 1436.336 ; gain = 223.395 Time (s): cpu = 00:00:40 ; elapsed = 00:00:30 . Memory (MB): peak = 1456.313 ; gain = 209.367
Post Restoration Checksum: NetGraph: 87f14705 NumContArr: 263c438d Constraints: 0 Timing: 0 Post Restoration Checksum: NetGraph: 97c7739f NumContArr: 666b03d3 Constraints: 0 Timing: 0
Phase 2 Router Initialization Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: ae2d8a92 Phase 2.1 Fix Topology Constraints | Checksum: fe327772
Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 1440.074 ; gain = 227.133 Time (s): cpu = 00:00:40 ; elapsed = 00:00:30 . Memory (MB): peak = 1460.750 ; gain = 213.805
Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: ae2d8a92 Phase 2.2 Pre Route Cleanup | Checksum: fe327772
Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 1440.074 ; gain = 227.133 Time (s): cpu = 00:00:40 ; elapsed = 00:00:30 . Memory (MB): peak = 1460.750 ; gain = 213.805
Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: fe327772
Phase 2 Router Initialization | Checksum: 6e1873f8
Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1448.008 ; gain = 235.066 Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1467.887 ; gain = 220.941
Phase 3 Initial Routing Phase 3 Initial Routing
Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 175100130
Phase 3 Initial Routing | Checksum: 6e1873f8
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496 Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1472.504 ; gain = 225.559
Phase 4 Rip-up And Reroute Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0
Phase 4.1 Global Iteration 0 | Checksum: 6e1873f8 Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: 16d0e9f58
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496 Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1472.504 ; gain = 225.559
Phase 4 Rip-up And Reroute | Checksum: 6e1873f8 Phase 4 Rip-up And Reroute | Checksum: 16d0e9f58
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496 Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1472.504 ; gain = 225.559
Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: 6e1873f8 Phase 5 Delay and Skew Optimization | Checksum: 16d0e9f58
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496 Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1472.504 ; gain = 225.559
Phase 6 Post Hold Fix Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: 6e1873f8 Phase 6.1 Hold Fix Iter | Checksum: 16d0e9f58
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496 Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1472.504 ; gain = 225.559
Phase 6 Post Hold Fix | Checksum: 6e1873f8 Phase 6 Post Hold Fix | Checksum: 16d0e9f58
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496 Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1472.504 ; gain = 225.559
Phase 7 Route finalize Phase 7 Route finalize
Router Utilization Summary Router Utilization Summary
Global Vertical Routing Utilization = 0 % Global Vertical Routing Utilization = 0.000156678 %
Global Horizontal Routing Utilization = 0 % Global Horizontal Routing Utilization = 0.000426257 %
Routable Net Status* Routable Net Status*
*Does not include unroutable nets such as driverless and loadless. *Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report. Run report_route_status for detailed report.
@@ -286,10 +355,10 @@ Router Utilization Summary
Number of Node Overlaps = 0 Number of Node Overlaps = 0
Congestion Report Congestion Report
North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. North Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0.900901%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
------------------------------ ------------------------------
Reporting congestion hotspots Reporting congestion hotspots
@@ -311,38 +380,38 @@ Direction: West
Congested clusters found at Level 0 Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: 6e1873f8 Phase 7 Route finalize | Checksum: 16d0e9f58
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1452.438 ; gain = 239.496 Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1472.504 ; gain = 225.559
Phase 8 Verifying routed nets Phase 8 Verifying routed nets
Verification completed successfully Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 6e1873f8 Phase 8 Verifying routed nets | Checksum: 16d0e9f58
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1454.441 ; gain = 241.500 Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1474.512 ; gain = 227.566
Phase 9 Depositing Routes Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 6e1873f8 Phase 9 Depositing Routes | Checksum: 122f3f6b5
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1454.441 ; gain = 241.500 Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1474.512 ; gain = 227.566
INFO: [Route 35-16] Router Completed Successfully INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:42 ; elapsed = 00:00:31 . Memory (MB): peak = 1454.441 ; gain = 241.500 Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1474.512 ; gain = 227.566
Routing Is Done. Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation INFO: [Common 17-83] Releasing license: Implementation
50 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. 49 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully route_design completed successfully
route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:32 . Memory (MB): peak = 1454.441 ; gain = 244.188 route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1474.512 ; gain = 227.566
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1454.441 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1474.512 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write. WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database... Writing placer database...
Writing XDEF routing. Writing XDEF routing.
Writing XDEF routing logical nets. Writing XDEF routing logical nets.
Writing XDEF routing special nets. Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1454.441 ; gain = 0.000 Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1474.512 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated. INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
Command: report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx Command: report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
@@ -364,7 +433,7 @@ INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation... Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation Finished Running Vector-less Activity Propagation
61 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. 60 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb INFO: [runtcl-4] Executing : report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
@@ -377,4 +446,4 @@ INFO: [runtcl-4] Executing : report_clock_utilization -file CPU9bits_clock_utili
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Wed Mar 13 11:13:49 2019... INFO: [Common 17-206] Exiting Vivado at Wed Mar 13 12:46:34 2019...

2
lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:49 2019 | Date : Wed Mar 13 12:46:34 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200) | Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx | Command : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx
| Design : CPU9bits | Design : CPU9bits

2
lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:49 2019 | Date : Wed Mar 13 12:46:34 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200) | Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt | Command : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt
| Design : CPU9bits | Design : CPU9bits

2
lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:14 2019 | Date : Wed Mar 13 12:46:00 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200) | Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt | Command : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt
| Design : CPU9bits | Design : CPU9bits

6
lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:13 2019 | Date : Wed Mar 13 12:45:55 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200) | Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx | Command : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx
| Design : CPU9bits | Design : CPU9bits
@@ -37,12 +37,12 @@ Table of Contents
----------------- -----------------
NSTD-1#1 Critical Warning NSTD-1#1 Critical Warning
Unspecified I/O Standard Unspecified I/O Standard
1 out of 1 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: done. 5 out of 5 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: instr[8], instr[7], instr[6], instr[5], done.
Related violations: <none> Related violations: <none>
UCIO-1#1 Critical Warning UCIO-1#1 Critical Warning
Unconstrained Logical Port Unconstrained Logical Port
1 out of 1 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: done. 5 out of 5 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: instr[8], instr[7], instr[6], instr[5], done.
Related violations: <none> Related violations: <none>
CFGBVS-1#1 Warning CFGBVS-1#1 Warning

6
lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:47 2019 | Date : Wed Mar 13 12:46:33 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200) | Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx | Command : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx
| Design : CPU9bits | Design : CPU9bits
@@ -37,12 +37,12 @@ Table of Contents
----------------- -----------------
NSTD-1#1 Critical Warning NSTD-1#1 Critical Warning
Unspecified I/O Standard Unspecified I/O Standard
1 out of 1 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: done. 5 out of 5 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: instr[8], instr[7], instr[6], instr[5], done.
Related violations: <none> Related violations: <none>
UCIO-1#1 Critical Warning UCIO-1#1 Critical Warning
Unconstrained Logical Port Unconstrained Logical Port
1 out of 1 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: done. 5 out of 5 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: instr[8], instr[7], instr[6], instr[5], done.
Related violations: <none> Related violations: <none>
CFGBVS-1#1 Warning CFGBVS-1#1 Warning

10
lab2CA.runs/impl_1/CPU9bits_io_placed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:14 2019 | Date : Wed Mar 13 12:46:00 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200) | Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_io -file CPU9bits_io_placed.rpt | Command : report_io -file CPU9bits_io_placed.rpt
| Design : CPU9bits | Design : CPU9bits
@@ -423,7 +423,7 @@ Table of Contents
| T12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | | T12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| T13 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | | T13 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| T14 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | | | T14 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | |
| T15 | | High Range | IO_L24P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | | T15 | instr[6] | High Range | IO_L24P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| T16 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | | T16 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T18 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | | T18 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
@@ -445,7 +445,7 @@ Table of Contents
| U12 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | | U12 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
| U13 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | | U13 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U15 | | High Range | IO_L24N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | | U15 | instr[5] | High Range | IO_L24N_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| U16 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | | U16 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| U17 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | | U17 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
| U18 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | | U18 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
@@ -467,7 +467,7 @@ Table of Contents
| V12 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | | V12 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| V13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | | V13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| V14 | done | High Range | IO_25_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | V14 | done | High Range | IO_25_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | |
| V15 | | High Range | IO_L23P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | | V15 | instr[8] | High Range | IO_L23P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | | V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | |
| V17 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | | V17 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
| V18 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | | V18 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
@@ -489,7 +489,7 @@ Table of Contents
| W12 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | | W12 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| W13 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | | W13 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
| W14 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | | W14 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
| W15 | | High Range | IO_L23N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | | W15 | instr[7] | High Range | IO_L23N_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| W16 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | | W16 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| W17 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | | W17 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |

2
lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:48 2019 | Date : Wed Mar 13 12:46:34 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200) | Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx | Command : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
| Design : CPU9bits | Design : CPU9bits

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lab2CA.runs/impl_1/CPU9bits_power_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:48 2019 | Date : Wed Mar 13 12:46:34 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200) | Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx | Command : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
| Design : CPU9bits | Design : CPU9bits
@@ -30,15 +30,15 @@ Table of Contents
---------- ----------
+--------------------------+--------------+ +--------------------------+--------------+
| Total On-Chip Power (W) | 0.084 | | Total On-Chip Power (W) | 0.476 |
| Design Power Budget (W) | Unspecified* | | Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA | | Power Budget Margin (W) | NA |
| Dynamic (W) | 0.000 | | Dynamic (W) | 0.389 |
| Device Static (W) | 0.084 | | Device Static (W) | 0.087 |
| Effective TJA (C/W) | 2.5 | | Effective TJA (C/W) | 2.5 |
| Max Ambient (C) | 99.8 | | Max Ambient (C) | 98.8 |
| Junction Temperature (C) | 25.2 | | Junction Temperature (C) | 26.2 |
| Confidence Level | High | | Confidence Level | Low |
| Setting File | --- | | Setting File | --- |
| Simulation Activity File | --- | | Simulation Activity File | --- |
| Design Nets Matched | NA | | Design Nets Matched | NA |
@@ -49,15 +49,16 @@ Table of Contents
1.1 On-Chip Components 1.1 On-Chip Components
---------------------- ----------------------
+--------------+-----------+----------+-----------+-----------------+ +----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) | | On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------+-----------+----------+-----------+-----------------+ +----------------+-----------+----------+-----------+-----------------+
| Slice Logic | 0.000 | 1 | --- | --- | | Slice Logic | 0.003 | 1 | --- | --- |
| Others | 0.000 | 1 | --- | --- | | LUT as Logic | 0.003 | 1 | 101400 | <0.01 |
| I/O | 0.000 | 1 | 285 | 0.35 | | Signals | 0.013 | 5 | --- | --- |
| Static Power | 0.084 | | | | | I/O | 0.373 | 5 | 285 | 1.75 |
| Total | 0.084 | | | | | Static Power | 0.087 | | | |
+--------------+-----------+----------+-----------+-----------------+ | Total | 0.476 | | | |
+----------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary 1.2 Power Supply Summary
@@ -66,11 +67,11 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+ +-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+ +-----------+-------------+-----------+-------------+------------+
| Vccint | 0.950 | 0.023 | 0.000 | 0.023 | | Vccint | 0.950 | 0.056 | 0.032 | 0.024 |
| Vccaux | 1.800 | 0.016 | 0.000 | 0.016 | | Vccaux | 1.800 | 0.046 | 0.029 | 0.016 |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | | Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | | Vcco18 | 1.800 | 0.171 | 0.170 | 0.001 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | | Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | | Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | | Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
@@ -86,17 +87,17 @@ Table of Contents
1.3 Confidence Level 1.3 Confidence Level
-------------------- --------------------
+-----------------------------+------------+------------------------------------------------+--------+ +-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action | | User Input Data | Confidence | Details | Action |
+-----------------------------+------------+------------------------------------------------+--------+ +-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | | | Design implementation state | High | Design is routed | |
| Clock nodes activity | High | User specified more than 95% of clocks | | | Clock nodes activity | High | User specified more than 95% of clocks | |
| I/O nodes activity | High | User specified more than 95% of inputs | | | I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | High | User specified more than 25% of internal nodes | | | Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | | | Device models | High | Device models are Production | |
| | | | | | | | | |
| Overall confidence level | High | | | | Overall confidence level | Low | | |
+-----------------------------+------------+------------------------------------------------+--------+ +-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
2. Settings 2. Settings
@@ -131,8 +132,11 @@ Table of Contents
3.1 By Hierarchy 3.1 By Hierarchy
---------------- ----------------
+------+-----------+ +----------+-----------+
| Name | Power (W) | | Name | Power (W) |
+------+-----------+ +----------+-----------+
| CPU9bits | 0.389 |
| CU | 0.007 |
+----------+-----------+

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lab2CA.runs/impl_1/CPU9bits_route_status.rpt
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Design Route Status Design Route Status
: # nets : : # nets :
------------------------------------------- : ----------- : ------------------------------------------- : ----------- :
# of logical nets.......................... : 2 : # of logical nets.......................... : 10 :
# of nets not needing routing.......... : 1 : # of nets not needing routing.......... : 5 :
# of internally routed nets........ : 1 : # of internally routed nets........ : 5 :
# of routable nets..................... : 1 : # of routable nets..................... : 5 :
# of fully routed nets............. : 1 : # of fully routed nets............. : 5 :
# of nets with routing errors.......... : 0 : # of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- : ------------------------------------------- : ----------- :

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lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:48 2019 | Date : Wed Mar 13 12:46:34 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200) | Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation | Command : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation
| Design : CPU9bits | Design : CPU9bits

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lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:14 2019 | Date : Wed Mar 13 12:46:00 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200) | Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb | Command : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb
| Design : CPU9bits | Design : CPU9bits
@@ -31,8 +31,8 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+ +-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+ +-------------------------+------+-------+-----------+-------+
| Slice LUTs | 0 | 0 | 101400 | 0.00 | | Slice LUTs | 1 | 0 | 101400 | <0.01 |
| LUT as Logic | 0 | 0 | 101400 | 0.00 | | LUT as Logic | 1 | 0 | 101400 | <0.01 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 | | LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 0 | 0 | 202800 | 0.00 | | Slice Registers | 0 | 0 | 202800 | 0.00 |
| Register as Flip Flop | 0 | 0 | 202800 | 0.00 | | Register as Flip Flop | 0 | 0 | 202800 | 0.00 |
@@ -67,10 +67,13 @@ Table of Contents
+------------------------------------------+------+-------+-----------+-------+ +------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+------------------------------------------+------+-------+-----------+-------+ +------------------------------------------+------+-------+-----------+-------+
| Slice | 0 | 0 | 25350 | 0.00 | | Slice | 1 | 0 | 25350 | <0.01 |
| SLICEL | 0 | 0 | | | | SLICEL | 1 | 0 | | |
| SLICEM | 0 | 0 | | | | SLICEM | 0 | 0 | | |
| LUT as Logic | 0 | 0 | 101400 | 0.00 | | LUT as Logic | 1 | 0 | 101400 | <0.01 |
| using O5 output only | 0 | | | |
| using O6 output only | 1 | | | |
| using O5 and O6 | 0 | | | |
| LUT as Memory | 0 | 0 | 35000 | 0.00 | | LUT as Memory | 0 | 0 | 35000 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | | | LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 0 | 0 | | | | LUT as Shift Register | 0 | 0 | | |
@@ -111,7 +114,9 @@ Table of Contents
+-----------------------------+------+-------+-----------+-------+ +-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+ +-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 1 | 0 | 285 | 0.35 | | Bonded IOB | 5 | 0 | 285 | 1.75 |
| IOB Master Pads | 2 | | | |
| IOB Slave Pads | 2 | | | |
| Bonded IPADs | 0 | 0 | 14 | 0.00 | | Bonded IPADs | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 8 | 0.00 | | Bonded OPADs | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 8 | 0.00 | | PHY_CONTROL | 0 | 0 | 8 | 0.00 |
@@ -172,7 +177,9 @@ Table of Contents
+----------+------+---------------------+ +----------+------+---------------------+
| Ref Name | Used | Functional Category | | Ref Name | Used | Functional Category |
+----------+------+---------------------+ +----------+------+---------------------+
| IBUF | 4 | IO |
| OBUF | 1 | IO | | OBUF | 1 | IO |
| LUT4 | 1 | LUT |
+----------+------+---------------------+ +----------+------+---------------------+

2
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1552489932"> <GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1552495493">
<File Type="BITSTR-BMM" Name="CPU9bits_bd.bmm"/> <File Type="BITSTR-BMM" Name="CPU9bits_bd.bmm"/>
<File Type="OPT-METHODOLOGY-DRC" Name="CPU9bits_methodology_drc_opted.rpt"/> <File Type="OPT-METHODOLOGY-DRC" Name="CPU9bits_methodology_drc_opted.rpt"/>
<File Type="INIT-TIMING" Name="CPU9bits_timing_summary_init.rpt"/> <File Type="INIT-TIMING" Name="CPU9bits_timing_summary_init.rpt"/>

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lab2CA.runs/impl_1/vivado.jou
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# Vivado v2018.3 (64-bit) # Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Mar 13 11:12:42 2019 # Start of session at: Wed Mar 13 12:45:23 2019
# Process ID: 11884 # Process ID: 13848
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1 # Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace # Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits.vdi # Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/CPU9bits.vdi

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lab2CA.runs/synth_1/CPU9bits.vds
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@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit) # Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Mar 13 11:12:14 2019 # Start of session at: Wed Mar 13 12:44:56 2019
# Process ID: 13200 # Process ID: 10868
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1 # Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl # Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.vds # Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.vds
@@ -15,56 +15,56 @@ Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti' Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 18016 INFO: Helper process launched with PID 9000
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 363.336 ; gain = 101.195 Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 364.543 ; gain = 101.914
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268] INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
INFO: [Synth 8-6155] done synthesizing module 'decoder' (1#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] INFO: [Synth 8-6155] done synthesizing module 'decoder' (1#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:774] INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
INFO: [Synth 8-6155] done synthesizing module 'register' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:774] INFO: [Synth 8-6155] done synthesizing module 'register' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:404] INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:409] INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412]
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:404] INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (4#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] INFO: [Synth 8-6155] done synthesizing module 'RegFile' (4#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (5#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (5#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (6#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (6#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:333] INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339] INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342]
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (7#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:333] INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (7#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (8#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (8#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3] INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:961] INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:964]
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026] INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1029]
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:684] INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (9#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:684] INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (9#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (10#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026] INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (10#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1029]
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (11#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:961] INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (11#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:964]
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:721] INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (12#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:721] INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (12#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:640] INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (13#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:640] INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (13#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (14#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (14#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:850] INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (15#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:850] INFO: [Synth 8-6155] done synthesizing module 'shift_left' (15#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:887] INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (16#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:887] INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (16#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:924] INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (17#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:924] INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (17#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:317] INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
INFO: [Synth 8-6155] done synthesizing module 'less_than' (18#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:317] INFO: [Synth 8-6155] done synthesizing module 'less_than' (18#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1075] INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1078]
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (19#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1075] INFO: [Synth 8-6155] done synthesizing module 'BEQ' (19#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1078]
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:532] INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:538] INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541]
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (20#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:532] INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (20#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
WARNING: [Synth 8-3848] Net result_L in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11] WARNING: [Synth 8-3848] Net result_L in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11] WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11] WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
@@ -73,37 +73,29 @@ WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver.
INFO: [Synth 8-6155] done synthesizing module 'ALU' (21#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3] INFO: [Synth 8-6155] done synthesizing module 'ALU' (21#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (22#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (22#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:347] INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:353] INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356]
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (23#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:347] INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (23#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
WARNING: [Synth 8-3848] Net dataMemOut in module/entity CPU9bits does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:8]
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (24#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (24#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0] WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0]
WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0] WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0]
WARNING: [Synth 8-3331] design shift_left has unconnected port A[8] WARNING: [Synth 8-3331] design shift_left has unconnected port A[8]
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.191 ; gain = 158.051 Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.887 ; gain = 158.258
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.191 ; gain = 158.051 Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.887 ; gain = 158.258
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Loading Part and Timing Information Start Loading Part and Timing Information
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Loading part: xc7k160tifbg484-2L Loading part: xc7k160tifbg484-2L
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.191 ; gain = 158.051 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.887 ; gain = 158.258
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
WARNING: [Synth 8-327] inferring latch for variable 'regOut_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:269]
WARNING: [Synth 8-327] inferring latch for variable 'aluOut_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:17]
WARNING: [Synth 8-327] inferring latch for variable 'FU_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:19]
WARNING: [Synth 8-327] inferring latch for variable 'addi_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:59]
WARNING: [Synth 8-327] inferring latch for variable 'mem_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:79]
WARNING: [Synth 8-327] inferring latch for variable 'RegEn_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:18]
WARNING: [Synth 8-327] inferring latch for variable 'halt_reg' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:89]
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.191 ; gain = 158.051 ---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.887 ; gain = 158.258
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@@ -123,10 +115,11 @@ Detailed RTL Component Info :
+---Muxes : +---Muxes :
4 Input 9 Bit Muxes := 2 4 Input 9 Bit Muxes := 2
2 Input 9 Bit Muxes := 5 2 Input 9 Bit Muxes := 5
2 Input 4 Bit Muxes := 1
4 Input 4 Bit Muxes := 1 4 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 2 2 Input 3 Bit Muxes := 2
13 Input 3 Bit Muxes := 1 13 Input 3 Bit Muxes := 1
13 Input 1 Bit Muxes := 6 13 Input 1 Bit Muxes := 4
2 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 1
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished RTL Component Statistics Finished RTL Component Statistics
@@ -138,6 +131,7 @@ Hierarchical RTL Component report
Module decoder Module decoder
Detailed RTL Component Info : Detailed RTL Component Info :
+---Muxes : +---Muxes :
2 Input 4 Bit Muxes := 1
4 Input 4 Bit Muxes := 1 4 Input 4 Bit Muxes := 1
Module register Module register
Detailed RTL Component Info : Detailed RTL Component Info :
@@ -160,7 +154,7 @@ Detailed RTL Component Info :
+---Muxes : +---Muxes :
2 Input 3 Bit Muxes := 2 2 Input 3 Bit Muxes := 2
13 Input 3 Bit Muxes := 1 13 Input 3 Bit Muxes := 1
13 Input 1 Bit Muxes := 6 13 Input 1 Bit Muxes := 4
Module bit1_mux_2_1 Module bit1_mux_2_1
Detailed RTL Component Info : Detailed RTL Component Info :
+---Muxes : +---Muxes :
@@ -182,24 +176,8 @@ No constraint files found.
Start Cross Boundary and Area Optimization Start Cross Boundary and Area Optimization
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met Warning: Parallel synthesis criteria is not met
INFO: [Synth 8-3333] propagating constant 1 across sequential element (\CU/halt_reg )
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[3]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[2]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[1]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (RF/d0/regOut_reg[0]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[3]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[2]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[1]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/aluOut_reg[0]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/FU_reg[2]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/FU_reg[1]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/FU_reg[0]) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/addi_reg) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/mem_reg) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/RegEn_reg) is unused and will be removed from module CPU9bits.
WARNING: [Synth 8-3332] Sequential element (CU/halt_reg) is unused and will be removed from module CPU9bits.
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 568.145 ; gain = 306.004 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 577.246 ; gain = 314.617
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@@ -212,7 +190,7 @@ No constraint files found.
Start Timing Optimization Start Timing Optimization
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 568.145 ; gain = 306.004 Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 577.246 ; gain = 314.617
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@@ -224,7 +202,7 @@ Report RTL Partitions:
Start Technology Mapping Start Technology Mapping
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 568.145 ; gain = 306.004 Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 577.246 ; gain = 314.617
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@@ -248,7 +226,7 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup Finished Final Netlist Cleanup
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004 Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report Check Netlist: Report Check Netlist:
@@ -261,7 +239,7 @@ Report Check Netlist:
Start Renaming Generated Instances Start Renaming Generated Instances
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004 Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@@ -273,25 +251,25 @@ Report RTL Partitions:
Start Rebuilding User Hierarchy Start Rebuilding User Hierarchy
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Renaming Generated Ports Start Renaming Generated Ports
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004 Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Handling Custom Attributes Start Handling Custom Attributes
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004 Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Renaming Generated Nets Start Renaming Generated Nets
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004 Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Writing Synthesis Report Start Writing Synthesis Report
@@ -307,35 +285,38 @@ Report Cell Usage:
+------+-----+------+ +------+-----+------+
| |Cell |Count | | |Cell |Count |
+------+-----+------+ +------+-----+------+
|1 |OBUF | 1| |1 |LUT4 | 1|
|2 |IBUF | 4|
|3 |OBUF | 1|
+------+-----+------+ +------+-----+------+
Report Instance Areas: Report Instance Areas:
+------+---------+-------+------+ +------+---------+------------+------+
| |Instance |Module |Cells | | |Instance |Module |Cells |
+------+---------+-------+------+ +------+---------+------------+------+
|1 |top | | 1| |1 |top | | 6|
+------+---------+-------+------+ |2 | CU |ControlUnit | 1|
+------+---------+------------+------+
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004 Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 31 warnings. Synthesis finished with 0 errors, 0 critical warnings and 8 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004 Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 568.145 ; gain = 306.004 Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist
INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 675.293 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.730 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary: INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed. No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis INFO: [Common 17-83] Releasing license: Synthesis
61 Infos, 31 Warnings, 0 Critical Warnings and 0 Errors encountered. 60 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully synth_design completed successfully
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 675.293 ; gain = 426.164 synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 681.730 ; gain = 431.730
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 675.293 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.730 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write. WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated. INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Wed Mar 13 11:12:35 2019... INFO: [Common 17-206] Exiting Vivado at Wed Mar 13 12:45:16 2019...

BIN
lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
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Binary file not shown.

10
lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:12:35 2019 | Date : Wed Mar 13 12:45:16 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200) | Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb | Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
| Design : CPU9bits | Design : CPU9bits
@@ -30,8 +30,8 @@ Table of Contents
+-------------------------+------+-------+-----------+-------+ +-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+ +-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 0 | 0 | 101400 | 0.00 | | Slice LUTs* | 1 | 0 | 101400 | <0.01 |
| LUT as Logic | 0 | 0 | 101400 | 0.00 | | LUT as Logic | 1 | 0 | 101400 | <0.01 |
| LUT as Memory | 0 | 0 | 35000 | 0.00 | | LUT as Memory | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 0 | 0 | 202800 | 0.00 | | Slice Registers | 0 | 0 | 202800 | 0.00 |
| Register as Flip Flop | 0 | 0 | 202800 | 0.00 | | Register as Flip Flop | 0 | 0 | 202800 | 0.00 |
@@ -90,7 +90,7 @@ Table of Contents
+-----------------------------+------+-------+-----------+-------+ +-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% | | Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+ +-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 1 | 0 | 285 | 0.35 | | Bonded IOB | 5 | 0 | 285 | 1.75 |
| Bonded IPADs | 0 | 0 | 14 | 0.00 | | Bonded IPADs | 0 | 0 | 14 | 0.00 |
| Bonded OPADs | 0 | 0 | 8 | 0.00 | | Bonded OPADs | 0 | 0 | 8 | 0.00 |
| PHY_CONTROL | 0 | 0 | 8 | 0.00 | | PHY_CONTROL | 0 | 0 | 8 | 0.00 |
@@ -151,7 +151,9 @@ Table of Contents
+----------+------+---------------------+ +----------+------+---------------------+
| Ref Name | Used | Functional Category | | Ref Name | Used | Functional Category |
+----------+------+---------------------+ +----------+------+---------------------+
| IBUF | 4 | IO |
| OBUF | 1 | IO | | OBUF | 1 | IO |
| LUT4 | 1 | LUT |
+----------+------+---------------------+ +----------+------+---------------------+

2
lab2CA.runs/synth_1/gen_run.xml
View File

@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1552489932"> <GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1552495493">
<File Type="PA-TCL" Name="CPU9bits.tcl"/> <File Type="PA-TCL" Name="CPU9bits.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_drc_synth.rpt"/> <File Type="RDS-PROPCONSTRS" Name="CPU9bits_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/> <File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>

4
lab2CA.runs/synth_1/vivado.jou
View File

@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit) # Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Mar 13 11:12:14 2019 # Start of session at: Wed Mar 13 12:44:56 2019
# Process ID: 13200 # Process ID: 10868
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1 # Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl # Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.vds # Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.vds

BIN
lab2CA.runs/synth_1/vivado.pb
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11
lab2CA.sim/sim_1/behav/xsim/CPU9bits_tb.tcl Normal file
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@@ -0,0 +1,11 @@
set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns

14
lab2CA.sim/sim_1/behav/xsim/CPU9bits_tb_vlog.prj Normal file
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@@ -0,0 +1,14 @@
# compile verilog/system verilog design source files
verilog xil_defaultlib \
"../../../../lab2CA.srcs/sources_1/new/ALU.v" \
"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
"../../../../lab2CA.srcs/sources_1/new/ControlUnit.v" \
"../../../../lab2CA.srcs/sources_1/new/FetchUnit.v" \
"../../../../lab2CA.srcs/sources_1/new/RegFile.v" \
"../../../../lab2CA.srcs/sources_1/new/CPU9bits.v" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort

14
lab2CA.sim/sim_1/behav/xsim/webtalk.jou
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@@ -2,11 +2,11 @@
# Webtalk v2018.3 (64-bit) # Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Tue Mar 12 20:38:16 2019 # Start of session at: Wed Mar 13 11:22:42 2019
# Process ID: 15148 # Process ID: 16888
# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim # Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou # Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#----------------------------------------------------------- #-----------------------------------------------------------
source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace source C:/Users/JoseIgnacio/CA -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_11840.backup.jou Normal file
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@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Mar 13 11:21:51 2019
# Process ID: 11840
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/JoseIgnacio/CA -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_12808.backup.jou Normal file
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@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Mar 13 11:21:19 2019
# Process ID: 12808
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/JoseIgnacio/CA -notrace

4
lab2CA.sim/sim_1/behav/xsim/webtalk_7548.backup.jou → lab2CA.sim/sim_1/behav/xsim/webtalk_15148.backup.jou
View File

@@ -2,8 +2,8 @@
# Webtalk v2018.3 (64-bit) # Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Tue Mar 12 20:36:54 2019 # Start of session at: Tue Mar 12 20:38:16 2019
# Process ID: 7548 # Process ID: 15148
# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim # Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log

12
lab2CA.sim/sim_1/behav/xsim/webtalk_17968.backup.jou Normal file
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@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Mar 13 11:20:32 2019
# Process ID: 17968
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/JoseIgnacio/CA -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_4236.backup.jou
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@@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Tue Mar 12 19:44:30 2019
# Process ID: 4236
# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_5116.backup.jou
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@@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Tue Mar 12 19:52:36 2019
# Process ID: 5116
# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_6512.backup.jou
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@@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Tue Mar 12 19:46:24 2019
# Process ID: 6512
# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace

BIN
lab2CA.sim/sim_1/behav/xsim/xelab.pb
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Binary file not shown.

1
lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/Compile_Options.txt Normal file
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@@ -0,0 +1 @@
-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "CPU9bits_tb_behav" "xil_defaultlib.CPU9bits_tb" "xil_defaultlib.glbl" -log "elaborate.log"

1
lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/TempBreakPointFile.txt Normal file
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@@ -0,0 +1 @@
Breakpoint File Version 1.0

155
lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c Normal file
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@@ -0,0 +1,155 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
extern void execute_2(char*, char *);
extern void execute_3(char*, char *);
extern void execute_135(char*, char *);
extern void execute_332(char*, char *);
extern void execute_333(char*, char *);
extern void execute_334(char*, char *);
extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*);
extern void execute_316(char*, char *);
extern void execute_317(char*, char *);
extern void execute_318(char*, char *);
extern void execute_320(char*, char *);
extern void execute_321(char*, char *);
extern void execute_322(char*, char *);
extern void execute_323(char*, char *);
extern void execute_324(char*, char *);
extern void execute_325(char*, char *);
extern void execute_326(char*, char *);
extern void execute_327(char*, char *);
extern void execute_328(char*, char *);
extern void execute_329(char*, char *);
extern void execute_330(char*, char *);
extern void execute_331(char*, char *);
extern void execute_140(char*, char *);
extern void execute_141(char*, char *);
extern void execute_142(char*, char *);
extern void execute_143(char*, char *);
extern void execute_144(char*, char *);
extern void execute_145(char*, char *);
extern void execute_146(char*, char *);
extern void execute_7(char*, char *);
extern void execute_9(char*, char *);
extern void execute_17(char*, char *);
extern void execute_166(char*, char *);
extern void execute_168(char*, char *);
extern void execute_169(char*, char *);
extern void execute_147(char*, char *);
extern void execute_148(char*, char *);
extern void execute_34(char*, char *);
extern void execute_278(char*, char *);
extern void execute_207(char*, char *);
extern void execute_188(char*, char *);
extern void execute_228(char*, char *);
extern void execute_229(char*, char *);
extern void execute_230(char*, char *);
extern void execute_231(char*, char *);
extern void execute_232(char*, char *);
extern void execute_233(char*, char *);
extern void execute_275(char*, char *);
extern void execute_276(char*, char *);
extern void execute_102(char*, char *);
extern void execute_104(char*, char *);
extern void execute_120(char*, char *);
extern void execute_137(char*, char *);
extern void execute_138(char*, char *);
extern void execute_139(char*, char *);
extern void execute_335(char*, char *);
extern void execute_336(char*, char *);
extern void execute_337(char*, char *);
extern void execute_338(char*, char *);
extern void execute_339(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[61] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_135, (funcp)execute_332, (funcp)execute_333, (funcp)execute_334, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_316, (funcp)execute_317, (funcp)execute_318, (funcp)execute_320, (funcp)execute_321, (funcp)execute_322, (funcp)execute_323, (funcp)execute_324, (funcp)execute_325, (funcp)execute_326, (funcp)execute_327, (funcp)execute_328, (funcp)execute_329, (funcp)execute_330, (funcp)execute_331, (funcp)execute_140, (funcp)execute_141, (funcp)execute_142, (funcp)execute_143, (funcp)execute_144, (funcp)execute_145, (funcp)execute_146, (funcp)execute_7, (funcp)execute_9, (funcp)execute_17, (funcp)execute_166, (funcp)execute_168, (funcp)execute_169, (funcp)execute_147, (funcp)execute_148, (funcp)execute_34, (funcp)execute_278, (funcp)execute_207, (funcp)execute_188, (funcp)execute_228, (funcp)execute_229, (funcp)execute_230, (funcp)execute_231, (funcp)execute_232, (funcp)execute_233, (funcp)execute_275, (funcp)execute_276, (funcp)execute_102, (funcp)execute_104, (funcp)execute_120, (funcp)execute_137, (funcp)execute_138, (funcp)execute_139, (funcp)execute_335, (funcp)execute_336, (funcp)execute_337, (funcp)execute_338, (funcp)execute_339, (funcp)vlog_transfunc_eventcallback};
const int NumRelocateId= 61;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/CPU9bits_tb_behav/xsim.reloc", (void **)funcTab, 61);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/CPU9bits_tb_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/CPU9bits_tb_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern void implicit_HDL_SCinstatiate();
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/CPU9bits_tb_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/CPU9bits_tb_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/CPU9bits_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

42
lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl Normal file
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@@ -0,0 +1,42 @@
webtalk_init -webtalk_dir C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Wed Mar 13 12:44:02 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "17336daf-0d92-4f07-b4a4-ff1c52043edb" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "32" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-3230M CPU @ 2.60GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "2594 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key File_Counter -value "7" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Simulation_Image_Code -value "90 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Image_Data -value "14 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Processes -value "227" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Instances -value "117" -context "xsim\\usage"
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Time -value "0.84_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Memory -value "42360_KB" -context "xsim\\usage"
webtalk_transmit -clientid 3756935279 -regid "" -xml C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

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1
lab2CA.srcs/sources_1/new/ALU.v
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@@ -11,6 +11,7 @@ module ALU(
wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H,result_I,result_J,result_K,result_L,result_M,result_N,result_O,result_P; wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H,result_I,result_J,result_K,result_L,result_M,result_N,result_O,result_P;
wire cout; wire cout;
// A (0000) - Add // A (0000) - Add
add_9bit add0( add_9bit add0(
.A(operand0), .A(operand0),
.B(operand1), .B(operand1),

17
lab2CA.srcs/sources_1/new/BasicModules.v
View File

@@ -264,14 +264,17 @@ module decoder (
output reg [3:0] regOut); output reg [3:0] regOut);
always @(en, index)begin always @(en, index)begin
if(en == 1)begin if(en == 0)begin
case(index) case(index)
2'b00: regOut <= 4'b0001; 2'b00: regOut <= 4'b1110;
2'b01: regOut <= 4'b0010; 2'b01: regOut <= 4'b1101;
2'b10: regOut <= 4'b0100; 2'b10: regOut <= 4'b1011;
2'b11: regOut <= 4'b1000; 2'b11: regOut <= 4'b0111;
default: regOut <= 4'b0000; default: regOut <= 4'b1111;
endcase endcase
end
else begin
regOut <= 4'b1111;
end end
end end
endmodule endmodule

26
lab2CA.srcs/sources_1/new/CPU9bits.v
View File

@@ -2,7 +2,8 @@
module CPU9bits(input wire [8:0] instr, module CPU9bits(input wire [8:0] instr,
input wire reset, clk, input wire reset, clk,
output wire done output wire done,
output wire [8:0] reg0
); );
wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut; wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;
@@ -54,7 +55,7 @@ module CPU9bits(input wire [8:0] instr,
add_9bit JBAdder( add_9bit JBAdder(
.A(PCout), .A(PCout),
.B(JBRes), .B(JBRes),
.Cin(9'b000000000), .Cin(1'b0),
.Sum(FUJB), .Sum(FUJB),
.Cout(cout0)); .Cout(cout0));
@@ -81,7 +82,7 @@ module CPU9bits(input wire [8:0] instr,
add_9bit Addier( add_9bit Addier(
.A({6'b000000,instr[2:0]}), .A({6'b000000,instr[2:0]}),
.B(op1), .B(op1),
.Cin(9'b000000000), .Cin(1'b0),
.Sum(AddiOut), .Sum(AddiOut),
.Cout(cout1)); .Cout(cout1));
@@ -93,7 +94,7 @@ module CPU9bits(input wire [8:0] instr,
mux_2_1 mux4( mux_2_1 mux4(
.A(loadMux), .A(loadMux),
.B(dataMemOut), .B(9'b000000001),
.out(RFIn), .out(RFIn),
.switch(loadS)); .switch(loadS));
@@ -119,22 +120,21 @@ module CPU9bits_tb();
.done(done)); .done(done));
initial begin initial begin
#5 reset = 1'b1;
reset = 0;
#10 #10
reset = 1; reset = 1'b0;
#10 #10
instruction = 000100000; instruction = 9'b000100000;
#10 #10
instruction = 000101001; instruction = 9'b000101000;
#10 #10
instruction = 010100010; instruction = 9'b010100010;
#10 #10
instruction = 111100000; instruction = 9'b111100000;
#10 #10
instruction = 111100000; instruction = 9'b111100000;
#10 #10
instruction = 000000000; instruction = 9'b000000000;
#10 #10
$finish; $finish;

68
lab2CA.srcs/sources_1/new/ControlUnit.v
View File

@@ -16,81 +16,133 @@ module ControlUnit(
if(functBit == 1) begin if(functBit == 1) begin
aluOut <= 4'b0001; //sub aluOut <= 4'b0001; //sub
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end end
else begin else begin
aluOut <= 4'b0000; //Add aluOut <= 4'b0000; //Add
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end end
4'b1101: begin 4'b1101: begin
aluOut <= 4'b0011; //nor aluOut <= 4'b0011; //nor
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end end
4'b1110: 4'b1110:
if(functBit == 1) begin if(functBit == 1) begin
aluOut <= 4'b0100; //and aluOut <= 4'b0100; //and
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end end
else begin else begin
aluOut <= 4'b0010; //or aluOut <= 4'b0010; //or
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end end
4'b1111: 4'b1111:
if(functBit == 1) begin if(functBit == 1) begin
aluOut <= 4'b0110; //srl aluOut <= 4'b0110; //srl
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end end
else begin else begin
aluOut <= 4'b0101; //shift left aluOut <= 4'b0101; //shift left
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end end
4'b0111: begin 4'b0111: begin
aluOut <= 4'b1001; //Less than aluOut <= 4'b1001; //Less than
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end end
4'b0110: begin 4'b0110: begin
aluOut <= 4'b0000;
addi <= 1'b1; // addi addi <= 1'b1; // addi
RegEn <= 1'b0; RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
end end
4'b1001: begin //We got it wrong, first bit must always be zero whenever branching happens. Fixed 4'b1001: begin //We got it wrong, first bit must always be zero whenever branching happens. Fixed
//FU <= 3'b010; // jump aluOut <= 4'b0000;
FU <= 3'b010; // jump FU <= 3'b010; // jump
RegEn <= 1'b1; RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end end
4'b1010: begin 4'b1010: begin
//FU <= 3'b011; // branch aluOut <= 4'b0000;
FU <= 3'b110; // branch FU <= 3'b110; // branch
RegEn <= 1'b1; RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end end
4'b1000: begin 4'b1000: begin
//FU <= 3'b001; // jumpreg aluOut <= 4'b0000;
FU <= 3'b000; // jumpreg FU <= 3'b000; // jumpreg
RegEn <= 1'b1; RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end end
4'b0001: begin 4'b0001: begin
mem <= 1'b0; // load aluOut <= 4'b0000;
mem <= 1'b1; // load
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
addi <= 1'b0;
halt <= 1'b0;
end end
4'b0010: begin 4'b0010: begin
mem <= 1'b1; // store aluOut <= 4'b0000;
mem <= 1'b0; // store
RegEn <= 1'b1; RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
end end
4'b0000: begin // regs should initialize at 0, so we shouldn't need to declare it everywhere 4'b0000: begin // regs should initialize at 0, so we shouldn't need to declare it everywhere
halt <= 1'b1; // halt halt <= 1'b1; // halt
RegEn <= 1'b1; RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
end end
default: aluOut <= 4'bxxxx; default: begin
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001;
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
end
endcase endcase
end end
endmodule endmodule

2
lab2CA.srcs/sources_1/new/FetchUnit.v
View File

@@ -19,7 +19,7 @@ module FetchUnit(input wire clk, reset,
add_9bit PCAdder( add_9bit PCAdder(
.A(progC_out), .A(progC_out),
.B(9'b000000001), .B(9'b000000001),
.Cin(9'b000000000), .Cin(1'b0),
.Sum(AddrOut), .Sum(AddrOut),
.Cout(cout)); .Cout(cout));

4
lab2CA.xpr
View File

@@ -31,7 +31,7 @@
<Option Name="EnableBDX" Val="FALSE"/> <Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/> <Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/> <Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="80"/> <Option Name="WTXSimLaunchSim" Val="114"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>
@@ -129,7 +129,7 @@
</File> </File>
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="comparator_tb"/> <Option Name="TopModule" Val="CPU9bits_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/> <Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/> <Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/> <Option Name="TransportIntDelay" Val="0"/>

66
regFile_tb_behav.wcfg
View File

@@ -3,69 +3,37 @@
<wave_state> <wave_state>
</wave_state> </wave_state>
<db_ref_list> <db_ref_list>
<db_ref path="regFile_tb_behav.wdb" id="1"> <db_ref path="CPU9bits_tb_behav.wdb" id="1">
<top_modules> <top_modules>
<top_module name="CPU9bits_tb" />
<top_module name="glbl" /> <top_module name="glbl" />
<top_module name="regFile_tb" />
</top_modules> </top_modules>
</db_ref> </db_ref>
</db_ref_list> </db_ref_list>
<zoom_setting> <zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime> <ZoomStartTime time="84990167fs"></ZoomStartTime>
<ZoomEndTime time="10131fs"></ZoomEndTime> <ZoomEndTime time="85010400fs"></ZoomEndTime>
<Cursor1Time time="0fs"></Cursor1Time> <Cursor1Time time="85000000fs"></Cursor1Time>
</zoom_setting> </zoom_setting>
<column_width_setting> <column_width_setting>
<NameColumnWidth column_width="127"></NameColumnWidth> <NameColumnWidth column_width="127"></NameColumnWidth>
<ValueColumnWidth column_width="136"></ValueColumnWidth> <ValueColumnWidth column_width="132"></ValueColumnWidth>
</column_width_setting> </column_width_setting>
<WVObjectSize size="12" /> <WVObjectSize size="4" />
<wvobject fp_name="/regFile_tb/write_d" type="array"> <wvobject fp_name="/CPU9bits_tb/instruction" type="array">
<obj_property name="ElementShortName">write_d[8:0]</obj_property> <obj_property name="ElementShortName">instruction[8:0]</obj_property>
<obj_property name="ObjectShortName">write_d[8:0]</obj_property> <obj_property name="ObjectShortName">instruction[8:0]</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/regFile_tb/w_idx" type="array"> <wvobject fp_name="/CPU9bits_tb/clk" type="logic">
<obj_property name="ElementShortName">w_idx[1:0]</obj_property>
<obj_property name="ObjectShortName">w_idx[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/op0_idx" type="array">
<obj_property name="ElementShortName">op0_idx[1:0]</obj_property>
<obj_property name="ObjectShortName">op0_idx[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/op1_idx" type="array">
<obj_property name="ElementShortName">op1_idx[1:0]</obj_property>
<obj_property name="ObjectShortName">op1_idx[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/reset" type="logic">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/op0" type="array">
<obj_property name="ElementShortName">op0[8:0]</obj_property>
<obj_property name="ObjectShortName">op0[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/op1" type="array">
<obj_property name="ElementShortName">op1[8:0]</obj_property>
<obj_property name="ObjectShortName">op1[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/clk" type="logic">
<obj_property name="ElementShortName">clk</obj_property> <obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property> <obj_property name="ObjectShortName">clk</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/regFile_tb/regFile0/r0_out" type="array"> <wvobject fp_name="/CPU9bits_tb/reset" type="logic">
<obj_property name="ElementShortName">r0_out[8:0]</obj_property> <obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">r0_out[8:0]</obj_property> <obj_property name="ObjectShortName">reset</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/regFile_tb/regFile0/r1_out" type="array"> <wvobject fp_name="/CPU9bits_tb/done" type="logic">
<obj_property name="ElementShortName">r1_out[8:0]</obj_property> <obj_property name="ElementShortName">done</obj_property>
<obj_property name="ObjectShortName">r1_out[8:0]</obj_property> <obj_property name="ObjectShortName">done</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/regFile0/r2_out" type="array">
<obj_property name="ElementShortName">r2_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r2_out[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/regFile_tb/regFile0/r3_out" type="array">
<obj_property name="ElementShortName">r3_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r3_out[8:0]</obj_property>
</wvobject> </wvobject>
</wave_config> </wave_config>