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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

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# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.runs/impl_1/gen_run.xml
#	lab2CA.sim/sim_1/behav/xsim/xelab.pb
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.sim/sim_1/behav/xsim/xvlog.pb
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
This commit is contained in:
Johannes
2019-04-11 21:55:30 -04:00
parent fa5e1d2739 0118debfb9
commit 15b58e43fb
10 changed files with 304 additions and 73 deletions
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2
lab2CA.srcs/sources_1/new/ControlUnit.v
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@@ -7,7 +7,7 @@ module ControlUnit(
output reg [2:0] FU,
output reg [1:0] bank,
output reg addi, mem, dataMemEn, RegEn, halt, link, js, compare0, compare1
);
);
always @(instIn, functBit)
begin

18
lab2CA.srcs/sources_1/new/instructionMemory.v
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@@ -5,18 +5,20 @@ module instructionMemory(
output reg [8:0] readData
);
reg [8:0] memory [6:0]; // Maximum of 512 memory locations
reg [8:0] memory [8:0]; // Maximum of 512 memory locations
// Vivado will give warnings of unconnected ports on the "address" bus if they are unused
initial begin
//Equation Solver
memory[0] <= 9'b000000000;
memory[1] <= 9'b000100000; //load
memory[2] <= 9'b000101000; //load
memory[3] <= 9'b010100010; //add
memory[4] <= 9'b111100000; //shift left
memory[5] <= 9'b000000001; //NOP
memory[6] <= 9'b111100000; //shift left
memory[0] <= 9'b000000000; //Stall
memory[1] <= 9'b000000000; //Stall
memory[2] <= 9'b011000000; //addi
memory[3] <= 9'b011001001; //addi
memory[4] <= 9'b000100000; //load
memory[5] <= 9'b000101010; //load
memory[6] <= 9'b010100010; //add
memory[7] <= 9'b111100000; //shift left
memory[8] <= 9'b111100000; //shift left
// //Testing all instructions
// memory[6] <= 9'b010100011; //sub