Instruction & Data Memory

2019-03-16 14:16:02 -04:00
parent dfd8753a62
commit 21e846ab62
27 changed files with 638 additions and 45 deletions
--- a/lab2CA.srcs/sources_1/new/dataMemory.v
+++ b/lab2CA.srcs/sources_1/new/dataMemory.v
@@ -0,0 +1,89 @@
+`timescale 1ns / 1ps
+
+module dataMemory(
+    input wire clk, writeEnable,
+    input wire [8:0] address, writeData,
+    output reg [8:0] readData
+    );
+    
+    reg [8:0] memory [15:0];
+    
+    initial begin
+        memory[0] <= 9'b000000000;
+        memory[1] <= 9'b000000000;
+        memory[2] <= 9'b000000000;
+        memory[3] <= 9'b000000000;
+        memory[4] <= 9'b000000000;
+        memory[5] <= 9'b000000000;
+        memory[6] <= 9'b000000000;
+        memory[7] <= 9'b000000000;
+        memory[8] <= 9'b000000000;
+        memory[9] <= 9'b000000000;
+        memory[10] <= 9'b000000000;
+        memory[11] <= 9'b000000000;
+        memory[12] <= 9'b000000000;
+        memory[13] <= 9'b000000000;
+        memory[14] <= 9'b000000000;
+        memory[15] <= 9'b000000000;
+    end
+
+    always@(address, posedge clk)begin
+        if(clk == 1'b1)begin
+        readData <= memory[address];
+        if(writeEnable == 1'b1)begin
+        memory[address] <= writeData;
+        end
+        else begin
+        memory[address] <= memory[address];
+        end
+        end
+    end      
+endmodule
+
+module dataMemory_tb();
+    reg clk, writeEnable;
+    reg [8:0] address, writeData;
+    wire [8:0] readData;
+    
+        initial begin
+        clk = 1'b0;
+    end
+    always begin
+        #5 clk = ~clk; // Period to be determined
+    end
+    
+    dataMemory dM0(
+        .clk(clk),
+        .writeEnable(writeEnable),
+        .writeData(writeData),
+        .address(address),
+        .readData(readData)
+    );
+    
+    initial begin
+        writeEnable = 1'b0;
+        address = 9'b000000000;
+        writeData = 9'b010101010;
+        #5
+        address = 9'b000000100;
+        writeData = 9'b010101010;
+        #10
+        writeEnable = 1'b1;
+        address = 9'b000000000;
+        writeData = 9'b010101010;
+        #10
+        address = 9'b000000001;
+        writeData = 9'b000001111;
+        #10
+        address = 9'b000000010;
+        writeData = 9'b000000101;
+        #10
+        address = 9'b000000011;
+        writeData = 9'b000000011;
+        #10
+        address = 9'b00000010;
+        writeData = 9'b000001101;
+        #5
+        $finish;
+    end
+endmodule