Instruction & Data Memory

lab2CA.srcs/sources_1/new/instructionMemory.v

@@ -0,0 +1,64 @@
+`timescale 1ns / 1ps
+
+module instructionMemory(
+    input wire clk,
+    input wire [8:0] address,
+    output reg [8:0] readData
+    );
+    
+    reg [8:0] memory [512:0];
+    
+    initial begin
+        //Equation Solver
+        memory[0] <= 9'b000100000;
+        memory[1] <= 9'b000101000;
+        memory[2] <= 9'b010100010;
+        memory[3] <= 9'b111100000;
+        memory[4] <= 9'b111100000;
+        memory[5] <= 9'b000000000;
+    end
+    
+    
+    always@(address, posedge clk)begin
+        readData <= memory[address];
+    end
+endmodule
+
+
+module instructionMemory_tb();
+    reg clk;
+    reg [8:0] address;
+    wire [8:0] readData;
+    
+        initial begin
+        clk = 1'b0;
+    end
+    always begin
+        #5 clk = ~clk; // Period to be determined
+    end
+    
+    instructionMemory iM0(
+        .clk(clk),
+        .address(address),
+        .readData(readData)
+    );
+    
+    initial begin
+        #10
+        address = 9'b000000000;
+        #5
+        address = 9'b000000001;
+        #5
+        address = 9'b000000010;
+        #5
+        address = 9'b000000011;
+        #5
+        address = 9'b000000100;
+        #5
+        address = 9'b000000101;
+        #5
+        address = 9'b000000111;
+        #5
+        $finish;
+    end
+endmodule