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Added pipeline registers

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This commit is contained in:
Johannes
2019-04-06 13:13:47 -04:00
parent 5353c8c22e
commit 2746d6d49c
9 changed files with 90 additions and 54 deletions
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34
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -850,6 +850,40 @@ module register_tb();
end
endmodule
module fDPipReg(
input wire clk,
input wire reset,
input wire En,
input wire [42:0] Din,
output reg [42:0] Dout);
always @(posedge clk) begin
if (reset == 1'b1) begin
Dout <= 23'b0000;
end
else if (En == 1'b0) begin
Dout <= Din;
end
end
endmodule
module eMPipReg(
input wire clk,
input wire reset,
input wire En,
input wire [42:0] Din,
output reg [42:0] Dout);
always @(posedge clk) begin
if (reset == 1'b1) begin
Dout <= 23'b0000;
end
else if (En == 1'b0) begin
Dout <= Din;
end
end
endmodule
module shift_left(
input wire [8:0] A,
output wire [8:0] B);

4
lab2CA.srcs/sources_1/new/dataMemory.v
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@@ -10,8 +10,8 @@ module dataMemory(
initial begin
//Equation Solver Memory
memory[0] <= 9'b000000001;
memory[1] <= 9'b000000010;
// memory[0] <= 9'b000000001;
// memory[1] <= 9'b000000010;
// String Compare Memory
// memory[0] <= 9'b000000100;

18
lab2CA.srcs/sources_1/new/instructionMemory.v
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@@ -10,15 +10,15 @@ module instructionMemory(
initial begin
//Equation Solver
memory[0] <= 9'b000000000;
memory[1] <= 9'b011000000; //add0
memory[1] <= 9'b011001001; //add1
memory[1] <= 9'b000100000; //load
memory[2] <= 9'b000101000; //load
memory[3] <= 9'b010100010; //add
memory[4] <= 9'b111100000; //shift left
memory[5] <= 9'b111100000; //shift left
memory[6] <= 9'b000000000; //halt
// memory[0] <= 9'b000000000;
// memory[1] <= 9'b011000000; //add0
// memory[1] <= 9'b011001001; //add1
// memory[1] <= 9'b000100000; //load
// memory[2] <= 9'b000101000; //load
// memory[3] <= 9'b010100010; //add
// memory[4] <= 9'b111100000; //shift left
// memory[5] <= 9'b111100000; //shift left
// memory[6] <= 9'b000000000; //halt
// //Testing all instructions
// memory[6] <= 9'b010100011; //sub