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Johannes 2746d6d49c Added pipeline registers
2019-04-06 13:13:47 -04:00
lab2CA.cache/wt
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2019-04-06 13:13:47 -04:00
lab2CA.ip_user_files
fetch unit
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lab2CA.runs
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Bank_behav1.wcfg
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CPU9bits_tb_behav.wcfg
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lab2CA.xpr
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README.md
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regFile_tb_behav.wcfg
Better Sim
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StringCompare.wcfg
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stuff
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new thing
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more stuff
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vivado.jou
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README.md

ECE 3570 Lab

Unknown Status of Fixes

  • Only two registers are being written to, first two within simulation is not being written to
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Description
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Readme 5.2 MiB
Languages
C 33.3%
Verilog 26.9%
PureBasic 23.7%
Tcl 16.1%