Added pipeline registers

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -850,6 +850,40 @@ module register_tb();
     end
 endmodule 
     
+module fDPipReg(
+        input wire clk, 
+	    input wire reset, 
+	    input wire En, 
+	    input wire [42:0] Din, 
+	    output reg [42:0] Dout);
+	    
+	    always @(posedge clk) begin
+		if (reset == 1'b1) begin
+			Dout <= 23'b0000;
+		end
+		else if (En == 1'b0) begin
+			Dout <= Din; 
+		end
+	end
+endmodule  
+
+module eMPipReg(  
+        input wire clk, 
+	    input wire reset, 
+	    input wire En, 
+	    input wire [42:0] Din, 
+	    output reg [42:0] Dout);
+	    
+	    always @(posedge clk) begin
+		if (reset == 1'b1) begin
+			Dout <= 23'b0000;
+		end
+		else if (En == 1'b0) begin
+			Dout <= Din; 
+		end
+	end
+endmodule 
+    
 module shift_left(
     input wire [8:0] A,
     output wire [8:0] B);