William/WMU-ECE-3570-Lab
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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

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# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.runs/impl_1/gen_run.xml
#	lab2CA.runs/synth_1/gen_run.xml
#	lab2CA.sim/sim_1/behav/xsim/xelab.pb
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.sim/sim_1/behav/xsim/xvlog.pb
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
This commit is contained in:
jose.rodriguezlabra
2019-03-24 14:17:59 -04:00
parent 94f0267a13 ee9e420365
commit 27f6d24b88
7 changed files with 160 additions and 149 deletions
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21
lab2CA.srcs/sources_1/new/dataMemory.v
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@@ -9,17 +9,18 @@ module dataMemory(
reg [8:0] memory [15:0];
initial begin
memory[0] <= 9'b000000000;
memory[1] <= 9'b000000000;
memory[2] <= 9'b000000000;
memory[3] <= 9'b000000000;
memory[4] <= 9'b000000000;
memory[5] <= 9'b000000000;
memory[6] <= 9'b000000000;
// String Compare Memory
memory[0] <= 9'b000000100;
memory[1] <= 9'b000001000;
memory[2] <= 9'b000001100;
memory[3] <= 9'b010101010;
memory[4] <= 9'b000001111;
memory[5] <= 9'b000000100;
memory[6] <= 9'b000000011;
memory[7] <= 9'b000000000;
memory[8] <= 9'b000000000;
memory[9] <= 9'b000000000;
memory[10] <= 9'b000000000;
memory[8] <= 9'b000001111;
memory[9] <= 9'b000000100;
memory[10] <= 9'b000000010;
memory[11] <= 9'b000000000;
memory[12] <= 9'b000000000;
memory[13] <= 9'b000000000;