Added zeroing instr

lab2CA.srcs/sources_1/new/ALU.v

@@ -65,6 +65,8 @@ module ALU(
         .A(operand0),
         .B(result_K));
     // L (1011)
+    // Will hacked in here
+    
     // M (1100)
     // N (1101)
     // O (1110)
@@ -84,7 +86,7 @@ module ALU(
         .I(result_I),
         .J(result_J),
         .K(result_K),
-        .L(result_L),
+        .L(9'b000000000),
         .M(result_M),
         .N(result_N),
         .O(result_O),

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -932,6 +932,7 @@ module shift_right_arithmetic(
 
 endmodule
 
+
 //testbench
 module shift_right_arithmetic_tb();
     reg [8:0] a;

lab2CA.srcs/sources_1/new/ControlUnit.v

@@ -41,6 +41,15 @@ module ControlUnit(
                      mem <= 1'b0;
                      link <= 1'b0;
                      end
+            4'b0100: begin 
+                     aluOut <= 4'b1011; //zero
+                     RegEn <= 1'b0;
+                     FU <= 3'b001; // Disable Branching
+                     halt <= 1'b0;
+                     addi <= 1'b0;
+                     mem <= 1'b0;
+                     link <= 1'b0;
+                     end
             4'b1110: 
                 if(functBit == 1) begin
                     aluOut <= 4'b0100; //and