Added zeroing instr

2019-03-16 14:34:36 -04:00
parent 21e846ab62
commit 3c8147641f
4 changed files with 25 additions and 13 deletions
--- a/lab2CA.srcs/sources_1/new/ControlUnit.v
+++ b/lab2CA.srcs/sources_1/new/ControlUnit.v
@@ -41,6 +41,15 @@ module ControlUnit(
                     mem <= 1'b0;
                     link <= 1'b0;
                     end
+            4'b0100: begin 
+                     aluOut <= 4'b1011; //zero
+                     RegEn <= 1'b0;
+                     FU <= 3'b001; // Disable Branching
+                     halt <= 1'b0;
+                     addi <= 1'b0;
+                     mem <= 1'b0;
+                     link <= 1'b0;
+                     end
            4'b1110: 
                if(functBit == 1) begin
                    aluOut <= 4'b0100; //and