Simplified testbench a little

lab2CA.srcs/sources_1/new/dataMemory.v

@@ -253,12 +253,8 @@ module dataMemory_tb();
     reg [8:0] address, writeData;
     wire [8:0] readData;
     
-        initial begin
+    always
-        clk = 1'b0;
-    end
-    always begin
         #5 clk = ~clk; // Period to be determined
-    end
     
     dataMemory dM0(
         .clk(clk),
@@ -268,7 +264,9 @@ module dataMemory_tb();
         .readData(readData)
     );
     
-    initial begin
+    initial
+    begin
+        clk = 1'b0;
         writeEnable = 1'b0;
         address = 9'b000000000;
         writeData = 9'b010101010;