CPU

LOTS
2019-03-10 16:32:25 -04:00
parent 7406cddb64
commit 460fc3e4ed
6 changed files with 191 additions and 61 deletions
--- a/lab2CA.srcs/sources_1/new/ALU.v
+++ b/lab2CA.srcs/sources_1/new/ALU.v
@@ -44,7 +44,7 @@ module ALU(
    shift_logical_right slr(
        .A(operand0),
        .B(result_G));
-    // H (111)
+    // H (111) //slt
    
    
    // MUX chooses which result to show based on the ALU's opcode