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Johannes
2019-03-10 16:32:25 -04:00
parent 7406cddb64
commit 460fc3e4ed
6 changed files with 191 additions and 61 deletions
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84
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -5,43 +5,87 @@ module CPU9bits(input wire [8:0] instr,
output reg done
);
wire [8:0] op1, op2;
wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;
wire [2:0] FU, aluOp;
wire addiS, RegEn, loadS;
RegFile RF(
.clk(clk),
.reset(reset),
.enable(),
.write_index(),
.op0_idx(),
.op1_idx(),
.write_data(),
.enable(RegEn),
.write_index(instr[4:3]),
.op0_idx(instr[4:3]),
.op1_idx(instr[2:1]),
.write_data(RFIn),
.op0(op0),
.op1(op1)
);
FetchUnit FU(
FetchUnit FetchU(
.clk(clk),
.reset(reset),
.op_idx(),
.AddrIn(),
.AddrOut()
.op_idx(FU[0]),
.AddrIn(FUAddr),
.AddrOut(PCout)
);
ALU alu(
.opcode(),
.opcode(aluOp),
.operand0(op0),
.operand1(op1),
.result()
.result(AluOut)
);
//Make control unit here
ControlUnit CU(
.instIn(instr[8:5]),
.functBit(instr[0]),
.aluOut(aluOp),
.FU(FU),
.addi(addiS),
.mem(loadS),
.load(loadMux)
);
always @(instr) begin
case (instr)
9'b000000000: //something
endcase
end
//------------------------------
//-----------------------Fetch Unit Stuff
add_9bit JBAdder(
.A(PCout),
.B(JBRes),
.Cin(9'b000000000),
.Sum(FUJB));
mux_2_1 mux1(
.A(op1),
.B(FUJB),
.out(FUAddr),
.switch(FU[1]));
mux_2_1 mux2(
.A({4'b0000,instr[4:0]}),
.B({6'b000000,instr[2:0]}),
.out(JBRes),
.switch(FU[2]));
///--------------------------Addi Stuff
add_9bit Addier(
.A({6'b000000,instr[2:0]}),
.B(op1),
.Cin(9'b000000000),
.Sum(AddiOut));
mux_2_1 mux3(
.A(AluOut),
.B(AddiOut),
.out(loadMux),
.switch(addiS));
mux_2_1 mux4(
.A(loadMux),
.B(dataMemOut),
.out(RFIn),
.switch(loadS));
endmodule
endmodule