CPU

LOTS
2019-03-10 16:32:25 -04:00
parent 7406cddb64
commit 460fc3e4ed
6 changed files with 191 additions and 61 deletions
--- a/lab2CA.srcs/sources_1/new/FetchUnit.v
+++ b/lab2CA.srcs/sources_1/new/FetchUnit.v
@@ -1,7 +1,7 @@
 `timescale 1ns / 1ps

 module FetchUnit(input wire clk, reset, 
-                 input wire [1:0] op_idx,
+                 input wire op_idx,
                 input wire [8:0] AddrIn,
                 output wire [8:0] AddrOut);