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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

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# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
#	lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
#	lab2CA.srcs/sources_1/new/instructionMemory.v
#	lab2CA.xpr
This commit is contained in:
jose.rodriguezlabra
2019-03-24 17:33:42 -04:00
parent efbd7b773b 033e606d5d
commit 5a506ba3ab
7 changed files with 280 additions and 64 deletions
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2
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -190,7 +190,7 @@ module CPU9bits_tb();
reset = 1'b1;
#10
reset = 1'b0;
#500
#850

86
lab2CA.srcs/sources_1/new/dataMemory.v
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@@ -9,6 +9,23 @@ module dataMemory(
reg [8:0] memory [15:0];
initial begin
// String Compare Memory
memory[0] <= 9'b000000100;
memory[1] <= 9'b000001000;
memory[2] <= 9'b000001100;
memory[3] <= 9'b010101010;
memory[4] <= 9'b000001111;
memory[5] <= 9'b000000100;
memory[6] <= 9'b000000011;
memory[7] <= 9'b000000111;
memory[8] <= 9'b000001111;
memory[9] <= 9'b000000100;
memory[10] <= 9'b000000010;
memory[11] <= 9'b000000000;
memory[12] <= 9'b000000000;
memory[13] <= 9'b000000000;
memory[14] <= 9'b000000000;
memory[15] <= 9'b000000000;
// // String Compare Memory
// memory[0] <= 9'b000000100;
// memory[1] <= 9'b000001000;
@@ -27,27 +44,54 @@ module dataMemory(
// memory[14] <= 9'b000000000;
// memory[15] <= 9'b000000000;
// Bubble Sort Initial Memory
memory[0] <= 9'b000011000;
memory[1] <= 9'b000000000;
memory[2] <= 9'b000100000;
memory[3] <= 9'b010001000;
memory[4] <= 9'b010010000;
memory[5] <= 9'b010011000;
memory[6] <= 9'b101001000;
memory[7] <= 9'b101001010;
memory[8] <= 9'b000100011;
memory[9] <= 9'b101001001;
memory[10] <= 9'b011001001;
memory[11] <= 9'b001001000;
memory[12] <= 9'b101001001;
memory[13] <= 9'b011101000;
memory[14] <= 9'b110001010;
memory[15] <= 9'b000100001;
memory[16] <= 9'b100110100;
memory[17] <= 9'b000001001;
memory[18] <= 9'b011001001;
memory[19] <= 9'b000110010;
memory[20] <= 9'b000000001;
memory[21] <= 9'b000111010;
memory[22] <= 9'b101011110;
memory[23] <= 9'b011111100;
// Binary Search Memory
memory[0] <= 9'b000000000;
memory[1] <= 9'b000000111;
memory[2] <= 9'b000000001;
memory[3] <= 9'b000000010;
memory[4] <= 9'b000000011;
memory[5] <= 9'b000000100;
memory[6] <= 9'b000000101;
memory[7] <= 9'b000000110;
memory[8] <= 9'b000000111;
memory[9] <= 9'b000001000;
memory[10] <= 9'b000001001;
memory[11] <= 9'b000001010;
memory[12] <= 9'b000001011;
memory[13] <= 9'b000001100;
memory[14] <= 9'b000001101;
memory[15] <= 9'b000001110;
memory[16] <= 9'b000001111;
memory[17] <= 9'b000010000;
memory[18] <= 9'b000010001;
memory[19] <= 9'b000010010;
// memory[0] <= 9'b000000000;
// memory[1] <= 9'b000000111;
// memory[2] <= 9'b000000001;
// memory[3] <= 9'b000000010;
// memory[4] <= 9'b000000011;
// memory[5] <= 9'b000000100;
// memory[6] <= 9'b000000101;
// memory[7] <= 9'b000000110;
// memory[8] <= 9'b000000111;
// memory[9] <= 9'b000001000;
// memory[10] <= 9'b000001001;
// memory[11] <= 9'b000001010;
// memory[12] <= 9'b000001011;
// memory[13] <= 9'b000001100;
// memory[14] <= 9'b000001101;
// memory[15] <= 9'b000001110;
// memory[16] <= 9'b000001111;
// memory[17] <= 9'b000010000;
// memory[18] <= 9'b000010001;
// memory[19] <= 9'b000010010;
end
@@ -110,4 +154,4 @@ module dataMemory_tb();
#5
$finish;
end
endmodule
endmodule

92
lab2CA.srcs/sources_1/new/instructionMemory.v
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@@ -34,6 +34,47 @@ module instructionMemory(
//String Compare
memory[0] <= 9'b000000000;
memory[1] <= 9'b010000000;
memory[2] <= 9'b010001000;
memory[3] <= 9'b010010000;
memory[4] <= 9'b010011000;
memory[5] <= 9'b000100000;
memory[6] <= 9'b011001001;
memory[7] <= 9'b000101010;
memory[8] <= 9'b011010010;
memory[9] <= 9'b000110100;
memory[10] <= 9'b011011011;
memory[11] <= 9'b000111110;
memory[12] <= 9'b101010000;
memory[13] <= 9'b101000010;
memory[14] <= 9'b101001100;
memory[15] <= 9'b101011110; //ends initialization
memory[16] <= 9'b101000011;
memory[17] <= 9'b101001101;
memory[18] <= 9'b000110000;
memory[19] <= 9'b000111010;
memory[20] <= 9'b110010001;
memory[21] <= 9'b100100001;
memory[22] <= 9'b100110000;
memory[23] <= 9'b110011001;
memory[24] <= 9'b100100001;
memory[25] <= 9'b100101101;
memory[26] <= 9'b011000001;
memory[27] <= 9'b011001001;
memory[28] <= 9'b101000010;
memory[29] <= 9'b101001100;
memory[30] <= 9'b010110111;
memory[31] <= 9'b110010001;
memory[32] <= 9'b101110001;
memory[33] <= 9'b101000001;
memory[34] <= 9'b101001111;
memory[35] <= 9'b001001000;
memory[36] <= 9'b011000001;
memory[37] <= 9'b101000000;
memory[38] <= 9'b101110111;
memory[39] <= 9'b000000000;
// memory[0] <= 9'b000000000;
// memory[1] <= 9'b010000000;
// memory[2] <= 9'b010001000;
@@ -75,6 +116,55 @@ module instructionMemory(
// memory[38] <= 9'b101111000;
// memory[39] <= 9'b000000000;
// Bubble Sort
memory[0] <= 9'b000000001;
memory[1] <= 9'b010000000;
memory[2] <= 9'b000100000;
memory[3] <= 9'b010001000;
memory[4] <= 9'b010010000;
memory[5] <= 9'b010011000;
memory[6] <= 9'b101001000;
memory[7] <= 9'b101001010;
memory[8] <= 9'b100100011;
memory[9] <= 9'b101001001;
memory[10] <= 9'b011001001;
memory[11] <= 9'b101001000;
memory[12] <= 9'b101001001;
memory[13] <= 9'b011101000;
memory[14] <= 9'b110001010;
memory[15] <= 9'b100100001;
memory[16] <= 9'b100110100;
memory[17] <= 9'b101001001;
memory[18] <= 9'b011001001;
memory[19] <= 9'b000110010;
memory[20] <= 9'b011001001;
memory[21] <= 9'b000111010;
memory[22] <= 9'b101011110;
memory[23] <= 9'b011111100;
memory[24] <= 9'b110011010;
memory[25] <= 9'b100100001;
memory[26] <= 9'b101110010;
memory[27] <= 9'b101001001;
memory[28] <= 9'b011001001;
memory[29] <= 9'b101011111;
memory[30] <= 9'b001011010;
memory[31] <= 9'b011001001;
memory[32] <= 9'b001010010;
memory[33] <= 9'b010001000;
memory[34] <= 9'b011001001;
memory[35] <= 9'b101001010;
memory[36] <= 9'b101111100;
memory[37] <= 9'b101001011;
memory[38] <= 9'b110001001;
memory[39] <= 9'b100100001;
memory[40] <= 9'b100100011;
memory[41] <= 9'b010001000;
memory[42] <= 9'b101001000;
memory[43] <= 9'b101111011;
memory[44] <= 9'b000000000;
// Binary Search
memory[0] <= 9'b000000000;
@@ -186,4 +276,4 @@ module instructionMemory_tb();
#5
$finish;
end
endmodule
endmodule