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Added link instruction

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This commit is contained in:
jose.rodriguezlabra
2019-03-16 14:01:32 -04:00
parent 934c73e899
commit 5cbe490aae
10 changed files with 225 additions and 61 deletions
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36
lab2CA.srcs/sources_1/new/CPU9bits.v
View File

@@ -6,10 +6,10 @@ module CPU9bits(
output wire done
);
wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;
wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData;
wire [2:0] FU;
wire [3:0] aluOp;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link;
RegFile RF(
.clk(clk),
@@ -46,7 +46,8 @@ module CPU9bits(
.addi(addiS),
.mem(loadS),
.RegEn(RegEn),
.halt(done)
.halt(done),
.link(link)
);
@@ -60,28 +61,28 @@ module CPU9bits(
.Cout(cout0));
mux_2_1 mux1(
.A(op1),
.A(op0),
.B(FUJB),
.out(FUAddr),
.switch(FU[1]));
mux_2_1 mux2(
.A({4'b0000,instr[4:0]}), //Jump
.B({6'b000000,instr[2:0]}),//Branch
.A({4'b0000,instr[4:0]}), //Jump -- Change with signer module!
.B({6'b000000,instr[2:0]}),//Branch -- Change with signer module!
.out(JBRes),
.switch(FU[2]));
bit1_mux_2_1 BranMux( // BEQ MUX
.A(FU[0]),
.B(op1[0]),
.B(op0[0]),
.out(fetchBranch),
.switch(FU[2])); // FU[2] only goes high when BEQ
///--------------------------Addi Stuff
add_9bit Addier(
.A({6'b000000,instr[2:0]}),
.B(op1),
.A({6'b000000,instr[2:0]}), // Change with signer module!
.B(op0),
.Cin(1'b0),
.Sum(AddiOut),
.Cout(cout1));
@@ -92,11 +93,22 @@ module CPU9bits(
.out(loadMux),
.switch(addiS));
///--------------------------Mem stuff
mux_2_1 mux4(
.A(loadMux),
.B(9'b000000001),
.A(linkData),
.B(9'b000000001), // This is DATA MEM
.out(RFIn),
.switch(loadS));
///--------------------------Link Stuff
mux_2_1 mux5(
.A(loadMux),
.B(PCout),
.out(linkData),
.switch(link));
endmodule
@@ -133,6 +145,8 @@ module CPU9bits_tb();
#10
instruction = 9'b111100000;
#10
instruction = 9'b001101000;
#10
instruction = 9'b000000000;
#10
$finish;

30
lab2CA.srcs/sources_1/new/ControlUnit.v
View File

@@ -8,7 +8,8 @@ module ControlUnit(
output reg addi,
output reg mem,
output reg RegEn,
output reg halt);
output reg halt,
output reg link);
always @(instIn, functBit)begin
case(instIn)
@@ -20,6 +21,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
end
else begin
aluOut <= 4'b0000; //Add
@@ -28,6 +30,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
end
4'b1101: begin
aluOut <= 4'b0011; //nor
@@ -36,6 +39,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
end
4'b1110:
if(functBit == 1) begin
@@ -45,6 +49,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
end
else begin
aluOut <= 4'b0010; //or
@@ -53,6 +58,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
end
4'b1111:
if(functBit == 1) begin
@@ -62,6 +68,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
end
else begin
aluOut <= 4'b0101; //shift left
@@ -70,6 +77,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
end
4'b0111: begin
aluOut <= 4'b1001; //Less than
@@ -78,6 +86,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
end
4'b0110: begin
aluOut <= 4'b0000;
@@ -86,14 +95,25 @@ module ControlUnit(
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
end
4'b1001: begin //We got it wrong, first bit must always be zero whenever branching happens. Fixed
4'b1001: begin
aluOut <= 4'b0000;
FU <= 3'b010; // jump
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
end
4'b0011: begin // link
halt <= 1'b0;
RegEn <= 1'b0;
FU <= 3'b001;
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b1;
end
4'b1010: begin
aluOut <= 4'b0000;
@@ -102,6 +122,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
end
4'b1000: begin
aluOut <= 4'b0000;
@@ -110,6 +131,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
link <= 1'b0;
end
4'b0001: begin
aluOut <= 4'b0000;
@@ -118,6 +140,7 @@ module ControlUnit(
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
halt <= 1'b0;
link <= 1'b0;
end
4'b0010: begin
aluOut <= 4'b0000;
@@ -126,6 +149,7 @@ module ControlUnit(
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
link <= 1'b0;
end
4'b0000: begin // regs should initialize at 0, so we shouldn't need to declare it everywhere
halt <= 1'b1; // halt
@@ -134,6 +158,7 @@ module ControlUnit(
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
end
default: begin
halt <= 1'b1;
@@ -142,6 +167,7 @@ module ControlUnit(
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
end
endcase
end