Added link instruction

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -6,10 +6,10 @@ module CPU9bits(
     output wire done
     );
     
-    wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;
+    wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData;
     wire [2:0] FU;
     wire [3:0] aluOp;
-    wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1;
+    wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link;
         
     RegFile RF(
         .clk(clk),
@@ -46,7 +46,8 @@ module CPU9bits(
         .addi(addiS),
         .mem(loadS),
         .RegEn(RegEn),
-        .halt(done)
+        .halt(done),
+        .link(link)
      );
      
      
@@ -60,28 +61,28 @@ module CPU9bits(
         .Cout(cout0));
         
     mux_2_1 mux1(
-        .A(op1),
+        .A(op0),
         .B(FUJB),
         .out(FUAddr),
         .switch(FU[1]));
         
     mux_2_1 mux2(
-        .A({4'b0000,instr[4:0]}), //Jump
-        .B({6'b000000,instr[2:0]}),//Branch
+        .A({4'b0000,instr[4:0]}), //Jump -- Change with signer module!
+        .B({6'b000000,instr[2:0]}),//Branch -- Change with signer module!
         .out(JBRes),
         .switch(FU[2]));
         
     bit1_mux_2_1 BranMux( // BEQ MUX
         .A(FU[0]),
-        .B(op1[0]),
+        .B(op0[0]),
         .out(fetchBranch),
         .switch(FU[2])); // FU[2] only goes high when BEQ
         
     ///--------------------------Addi Stuff
         
     add_9bit Addier(
-        .A({6'b000000,instr[2:0]}),
-        .B(op1),
+        .A({6'b000000,instr[2:0]}), // Change with signer module!
+        .B(op0),
         .Cin(1'b0),
         .Sum(AddiOut),
         .Cout(cout1));
@@ -92,11 +93,22 @@ module CPU9bits(
         .out(loadMux),
         .switch(addiS));
         
+        
+    ///--------------------------Mem stuff
+        
     mux_2_1 mux4(
-        .A(loadMux),
-        .B(9'b000000001),
+        .A(linkData),
+        .B(9'b000000001), // This is DATA MEM
         .out(RFIn),
         .switch(loadS));
+        
+    ///--------------------------Link Stuff
+    
+    mux_2_1 mux5(
+        .A(loadMux),
+        .B(PCout),
+        .out(linkData),
+        .switch(link));
      
          
 endmodule
@@ -133,6 +145,8 @@ module CPU9bits_tb();
         #10
         instruction = 9'b111100000;
         #10
+        instruction = 9'b001101000;
+        #10
         instruction = 9'b000000000;
         #10    
         $finish;