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Johannes
2019-04-06 17:54:50 -04:00
parent e6cb8e536b e937485bd4
commit 616dac4d29
31 changed files with 899 additions and 525 deletions
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306
lab2CA.srcs/sources_1/new/ControlUnit.v
View File

@@ -13,71 +13,72 @@ module ControlUnit(
case(instIn)
4'b0000: // Halt/NOP
begin
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0001: // Load Byte
begin
aluOut <= 4'b0000;
mem <= 1'b1;
dataMemEn <= 1'b0; // Disabled
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
halt <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b1;
dataMemEn <= 1'b0; // Disabled
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
halt <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0010: // Store Byte
begin
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b1; // Enabled
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b1; // Enabled
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0011: // Link
begin
halt <= 1'b0;
RegEn <= 1'b0;
FU <= 3'b001;
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b1;
bank <= 2'b10;
js <= 1'b0;
halt <= 1'b0;
RegEn <= 1'b0;
FU <= 3'b001;
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b1;
bank <= 2'b10;
js <= 1'b0;
end
4'b0100: // Zero
begin
aluOut <= 4'b1011;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b1011;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0101: // Add/Subtract
if(functBit == 1) begin // Subtract
if(functBit == 1) // Subtract
begin
aluOut <= 4'b0001;
RegEn <= 1'b0;
FU <= 3'b001;
@@ -88,8 +89,9 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
else begin // Add
end
else // Add
begin
aluOut <= 4'b0000;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
@@ -100,114 +102,114 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
end
4'b0110: // Add Immediate
begin
aluOut <= 4'b1010;
addi <= 1'b1;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b1010;
addi <= 1'b1;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b0111: // Set if Less Than
begin
aluOut <= 4'b1001;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b1001;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1000: // Jump to Register
begin
aluOut <= 4'b0000;
FU <= 3'b000;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b0000;
FU <= 3'b000;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1001: // Jump Forward
begin
aluOut <= 4'b0000;
FU <= 3'b010;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b0000;
FU <= 3'b010;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1010: // Bank Load/Bank Store
begin
halt <= 1'b0;
RegEn <= !functBit;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
aluOut <= 4'b0000;
dataMemEn <= 1'b0; // Disabled
mem <= 1'b0;
link <= 1'b0;
bank <= {functBit,functBit};
js <= 1'b0;
halt <= 1'b0;
RegEn <= !functBit;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
aluOut <= 4'b0000;
dataMemEn <= 1'b0; // Disabled
mem <= 1'b0;
link <= 1'b0;
bank <= {functBit,functBit};
js <= 1'b0;
end
4'b1011: // Jump Backward
begin
aluOut <= 4'b0000;
FU <= 3'b010;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b1;
aluOut <= 4'b0000;
FU <= 3'b010;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b1;
end
4'b1100: // Branch if Zero
begin
aluOut <= 4'b1010;
FU <= 3'b110;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b1010;
FU <= 3'b110;
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1101: // NOR
begin
aluOut <= 4'b0011;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
aluOut <= 4'b0011;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
4'b1110: // OR/AND
if(functBit == 1) // AND
begin
begin
aluOut <= 4'b0100;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
@@ -218,9 +220,9 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
end
else // OR
begin
begin
aluOut <= 4'b0010;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
@@ -231,10 +233,10 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
end
4'b1111: // Shift Right Logical/Shift Left Logical
if(functBit == 1) // Shift Right Logical
begin
begin
aluOut <= 4'b0110;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
@@ -245,9 +247,9 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
end
else // Shift Left Logical
begin
begin
aluOut <= 4'b0101;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
@@ -258,19 +260,19 @@ module ControlUnit(
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
end
default:
begin
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001;
dataMemEn <= 1'b0; // Disabled
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001;
dataMemEn <= 1'b0; // Disabled
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
end
endcase
end

11
lab2CA.srcs/sources_1/new/FetchUnit.v
View File

@@ -1,9 +1,11 @@
`timescale 1ns / 1ps
module FetchUnit(input wire clk, reset,
input wire op_idx,
input wire [8:0] AddrIn,
output wire [8:0] AddrOut);
module FetchUnit(
input wire clk, reset,
input wire op_idx,
input wire [8:0] AddrIn,
output wire [8:0] AddrOut
);
//Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a)
wire [8:0] progC_out, result_m;
@@ -29,7 +31,6 @@ module FetchUnit(input wire clk, reset,
.out(result_m),
.switch(op_idx));
endmodule
//testbench

204
lab2CA.srcs/sources_1/new/dataMemory.v
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@@ -6,7 +6,7 @@ module dataMemory(
output reg [8:0] readData
);
reg [8:0] memory [512:0]; // Maximum of 512 memory locations
reg [8:0] memory [100:0]; // Maximum of 512 memory locations
// Vivado will give warnings of unconnected ports on the "address" bus if they are unused
initial begin
@@ -97,107 +97,107 @@ module dataMemory(
// Program 1 Test Data
// memory[0] <= 9'd100;
// memory[1] <= 9'd58;
// memory[2] <= 9'd6;
// memory[3] <= 9'd12;
// memory[4] <= 9'b110110000; // -80
// memory[5] <= 9'd17;
// memory[6] <= 9'b111011011; // -37
// memory[7] <= 9'd25;
// memory[8] <= -9'd83; // -83
// memory[9] <= -9'd98; // -98
// memory[10] <= -9'd98; // -98
// memory[11] <= -9'd74; // -74
// memory[12] <= 9'd70;
// memory[13] <= -9'd38; // -38
// memory[14] <= 9'd52;
// memory[15] <= -9'd96; // -96
// memory[16] <= -9'd32; // -32
// memory[17] <= -9'd93; // -93
// memory[18] <= -9'd40; // -40
// memory[19] <= 9'd59;
// memory[20] <= 9'd10;
// memory[21] <= 9'd81;
// memory[22] <= -9'd23; // -28
// memory[23] <=- 9'd99; // -99
// memory[24] <= -9'd41; // -41
// memory[25] <= 9'd33;
// memory[26] <= 9'd98;
// memory[27] <= 9'd73;
// memory[28] <= -9'd1; // -1
// memory[29] <= 9'd28;
// memory[30] <= 9'd5;
// memory[31] <= -9'd74; // -74
// memory[32] <= -9'd41; // -41
// memory[33] <= 9'd41;
// memory[34] <= 9'd39;
// memory[35] <= 9'd62;
// memory[36] <= 9'd19;
// memory[37] <= -9'd40; // -40
// memory[38] <= -9'd8; // -8
// memory[39] <= 9'd92;
// memory[40] <= 9'd37;
// memory[41] <= 9'd50;
// memory[42] <= -9'd72; // -72
// memory[43] <= -9'd5; // -5
// memory[44] <= 9'd19;
// memory[45] <= 9'd58;
// memory[46] <= -9'd13; // -13
// memory[47] <= 9'd0;
// memory[48] <= -9'd97; // -97
// memory[49] <= 9'd54;
// memory[50] <= -9'd17; // -17
// memory[51] <= -9'd83; // -83
// memory[52] <= 9'd53;
// memory[53] <= 9'd82;
// memory[54] <= -9'd94; // -94
// memory[55] <= -9'd77; // -77
// memory[56] <= -9'd74; // -74
// memory[57] <= -9'd52; // -52
// memory[58] <= 9'd85;
// memory[59] <= -9'd65; // -65
// memory[60] <= -9'd10; // -10
// memory[61] <= -9'd45; // -45
// memory[62] <= -9'd92; // -92
// memory[63] <= -9'd30; // -30
// memory[64] <= 9'd18;
// memory[65] <= -9'd95; // -95
// memory[66] <= -9'd27; // -27
// memory[67] <= -9'd74; // -74
// memory[68] <= 9'd62;
// memory[69] <= 9'd64;
// memory[70] <= -9'd9; // -9
// memory[71] <= 9'd66;
// memory[72] <= -9'd71; // -71
// memory[73] <= -9'd31; // -31
// memory[74] <= 9'd34;
// memory[75] <= 9'd12;
// memory[76] <= 9'd3;
// memory[77] <= 9'd82;
// memory[78] <= 9'd13;
// memory[79] <= -9'd78; // -78
// memory[80] <= -9'd8; // -8
// memory[81] <= 9'd88;
// memory[82] <= 9'd42;
// memory[83] <= 9'd42;
// memory[84] <= 9'd21;
// memory[85] <= -9'd44; // -44
// memory[86] <= 9'd30;
// memory[87] <= -9'd93; // -93
// memory[88] <= 9'd2;
// memory[89] <= -9'd34; // -34
// memory[90] <= 9'd92;
// memory[91] <= -9'd45; // -45
// memory[92] <= 9'd26;
// memory[93] <= -9'd79; // -79
// memory[94] <= 9'd43;
// memory[95] <= -9'd25; // -25
// memory[96] <= -9'd24; // -24
// memory[97] <= -9'd25; // -25
// memory[98] <= -9'd19; // -19
// memory[99] <= -9'd49; // -49
// memory[100] <= -9'd8; // -8
memory[0] <= 9'd100;
memory[1] <= 9'd58;
memory[2] <= 9'd6;
memory[3] <= 9'd12;
memory[4] <= 9'b110110000; // -80
memory[5] <= 9'd17;
memory[6] <= 9'b111011011; // -37
memory[7] <= 9'd25;
memory[8] <= -9'd83; // -83
memory[9] <= -9'd98; // -98
memory[10] <= -9'd98; // -98
memory[11] <= -9'd74; // -74
memory[12] <= 9'd70;
memory[13] <= -9'd38; // -38
memory[14] <= 9'd52;
memory[15] <= -9'd96; // -96
memory[16] <= -9'd32; // -32
memory[17] <= -9'd93; // -93
memory[18] <= -9'd40; // -40
memory[19] <= 9'd59;
memory[20] <= 9'd10;
memory[21] <= 9'd81;
memory[22] <= -9'd23; // -28
memory[23] <=- 9'd99; // -99
memory[24] <= -9'd41; // -41
memory[25] <= 9'd33;
memory[26] <= 9'd98;
memory[27] <= 9'd73;
memory[28] <= -9'd1; // -1
memory[29] <= 9'd28;
memory[30] <= 9'd5;
memory[31] <= -9'd74; // -74
memory[32] <= -9'd41; // -41
memory[33] <= 9'd41;
memory[34] <= 9'd39;
memory[35] <= 9'd62;
memory[36] <= 9'd19;
memory[37] <= -9'd40; // -40
memory[38] <= -9'd8; // -8
memory[39] <= 9'd92;
memory[40] <= 9'd37;
memory[41] <= 9'd50;
memory[42] <= -9'd72; // -72
memory[43] <= -9'd5; // -5
memory[44] <= 9'd19;
memory[45] <= 9'd58;
memory[46] <= -9'd13; // -13
memory[47] <= 9'd0;
memory[48] <= -9'd97; // -97
memory[49] <= 9'd54;
memory[50] <= -9'd17; // -17
memory[51] <= -9'd83; // -83
memory[52] <= 9'd53;
memory[53] <= 9'd82;
memory[54] <= -9'd94; // -94
memory[55] <= -9'd77; // -77
memory[56] <= -9'd74; // -74
memory[57] <= -9'd52; // -52
memory[58] <= 9'd85;
memory[59] <= -9'd65; // -65
memory[60] <= -9'd10; // -10
memory[61] <= -9'd45; // -45
memory[62] <= -9'd92; // -92
memory[63] <= -9'd30; // -30
memory[64] <= 9'd18;
memory[65] <= -9'd95; // -95
memory[66] <= -9'd27; // -27
memory[67] <= -9'd74; // -74
memory[68] <= 9'd62;
memory[69] <= 9'd64;
memory[70] <= -9'd9; // -9
memory[71] <= 9'd66;
memory[72] <= -9'd71; // -71
memory[73] <= -9'd31; // -31
memory[74] <= 9'd34;
memory[75] <= 9'd12;
memory[76] <= 9'd3;
memory[77] <= 9'd82;
memory[78] <= 9'd13;
memory[79] <= -9'd78; // -78
memory[80] <= -9'd8; // -8
memory[81] <= 9'd88;
memory[82] <= 9'd42;
memory[83] <= 9'd42;
memory[84] <= 9'd21;
memory[85] <= -9'd44; // -44
memory[86] <= 9'd30;
memory[87] <= -9'd93; // -93
memory[88] <= 9'd2;
memory[89] <= -9'd34; // -34
memory[90] <= 9'd92;
memory[91] <= -9'd45; // -45
memory[92] <= 9'd26;
memory[93] <= -9'd79; // -79
memory[94] <= 9'd43;
memory[95] <= -9'd25; // -25
memory[96] <= -9'd24; // -24
memory[97] <= -9'd25; // -25
memory[98] <= -9'd19; // -19
memory[99] <= -9'd49; // -49
memory[100] <= -9'd8; // -8

143
lab2CA.srcs/sources_1/new/instructionMemory.v
View File

@@ -5,16 +5,17 @@ module instructionMemory(
output reg [8:0] readData
);
reg [8:0] memory [512:0];
reg [8:0] memory [100:0]; // Maximum of 512 memory locations
// Vivado will give warnings of unconnected ports on the "address" bus if they are unused
initial begin
//Equation Solver
memory[0] <= 9'b000000000;
memory[1] <= 9'b000100000; //load
memory[2] <= 9'b000101000; //load
memory[3] <= 9'b010100010; //add
memory[4] <= 9'b111100000; //shift left
memory[5] <= 9'b111100000; //shift left
// //Equation Solver
// memory[0] <= 9'b000000000;
// memory[1] <= 9'b000100000; //load
// memory[2] <= 9'b000101000; //load
// memory[3] <= 9'b010100010; //add
// memory[4] <= 9'b111100000; //shift left
// memory[5] <= 9'b111100000; //shift left
// //Testing all instructions
// memory[6] <= 9'b010100011; //sub
@@ -75,69 +76,69 @@ module instructionMemory(
// memory[39] <= 9'b000000000;
// Bubble Sort
// memory[0] <= 9'b000000001; // nop
// // Setup
// memory[1] <= 9'b010000000; // zero $a
// memory[2] <= 9'b000100000; // lb $a, $a
// memory[3] <= 9'b010001000; // zero $b
// memory[4] <= 9'b010010000; // zero $c
// memory[5] <= 9'b010011000; // zero $d
// memory[6] <= 9'b101001000; // banks $b, $0
// memory[7] <= 9'b101001010; // banks $b, $1
// memory[8] <= 9'b100100011; // jf EndChk
// // Increment current index to compare next pair of values
// // Inc:
// memory[9] <= 9'b101001001; // bankl $b, $0
// memory[10] <= 9'b011001001; // addi $b, 1
// memory[11] <= 9'b101001000; // banks $b, $0
// // Check if at the end of the array
// // EndChk:
// memory[12] <= 9'b101001001; // bankl $b, $0
// memory[13] <= 9'b011101000; // slt $b, $a
// memory[14] <= 9'b110001001; // beq $b, JSC
// memory[15] <= 9'b100100001; // jf LoadNext
// // JSC:
// memory[16] <= 9'b100110100; // jf SwapChk
// // Load next values for comparison
// // LoadNext:
// memory[17] <= 9'b101001001; // bankl $b, $0
// memory[18] <= 9'b011001001; // addi $b, 1
// memory[19] <= 9'b000110010; // lb $c, $b
// memory[20] <= 9'b011001001; // addi $b, 1
// memory[21] <= 9'b000111010; // lb $d, $b
// // Compare loaded values to see if they need to be swapped
// memory[22] <= 9'b101011110; // banks $d, $3
// memory[23] <= 9'b011111100; // slt $d, $c
// memory[24] <= 9'b110011001; // beq $d, JI
// memory[25] <= 9'b100100001; // jf Swap
// // JI:
// memory[26] <= 9'b101110010; // jb Inc
// // Swap values in array
// // Swap:
// memory[27] <= 9'b101001001; // bankl $b, $0
// memory[28] <= 9'b011001001; // addi $b, 1
// memory[29] <= 9'b101011111; // bankl $d, $3
// memory[30] <= 9'b001011010; // sb $d, $b
// memory[31] <= 9'b011001001; // addi $b, 1
// memory[32] <= 9'b001010010; // sb $c, $b
// memory[33] <= 9'b010001000; // zero $b
// memory[34] <= 9'b011001001; // addi $b, 1
// memory[35] <= 9'b101001010; // banks $b, $1
// memory[36] <= 9'b101111100; // jb Inc
// // Check to see if any swaps have been made in the last iteration
// // SwapChk:
// memory[37] <= 9'b101001011; // bankl $b, $1
// memory[38] <= 9'b110001001; // beq $b, JE
// memory[39] <= 9'b100100001; // jf Reset
// // JE:
// memory[40] <= 9'b100100011; // jf End
// // Reset:
// memory[41] <= 9'b010001000; // zero $b
// memory[42] <= 9'b101001000; // banks $b, $0
// memory[43] <= 9'b101111011; // jb LoadNext
// // End:
// memory[44] <= 9'b000000000; // halt
//Bubble Sort
memory[0] <= 9'b000000001; // nop
// Setup
memory[1] <= 9'b010000000; // zero $a
memory[2] <= 9'b000100000; // lb $a, $a
memory[3] <= 9'b010001000; // zero $b
memory[4] <= 9'b010010000; // zero $c
memory[5] <= 9'b010011000; // zero $d
memory[6] <= 9'b101001000; // banks $b, $0
memory[7] <= 9'b101001010; // banks $b, $1
memory[8] <= 9'b100100011; // jf EndChk
// Increment current index to compare next pair of values
// Inc:
memory[9] <= 9'b101001001; // bankl $b, $0
memory[10] <= 9'b011001001; // addi $b, 1
memory[11] <= 9'b101001000; // banks $b, $0
// Check if at the end of the array
// EndChk:
memory[12] <= 9'b101001001; // bankl $b, $0
memory[13] <= 9'b011101000; // slt $b, $a
memory[14] <= 9'b110001001; // beq $b, JSC
memory[15] <= 9'b100100001; // jf LoadNext
// JSC:
memory[16] <= 9'b100110100; // jf SwapChk
// Load next values for comparison
// LoadNext:
memory[17] <= 9'b101001001; // bankl $b, $0
memory[18] <= 9'b011001001; // addi $b, 1
memory[19] <= 9'b000110010; // lb $c, $b
memory[20] <= 9'b011001001; // addi $b, 1
memory[21] <= 9'b000111010; // lb $d, $b
// Compare loaded values to see if they need to be swapped
memory[22] <= 9'b101011110; // banks $d, $3
memory[23] <= 9'b011111100; // slt $d, $c
memory[24] <= 9'b110011001; // beq $d, JI
memory[25] <= 9'b100100001; // jf Swap
// JI:
memory[26] <= 9'b101110010; // jb Inc
// Swap values in array
// Swap:
memory[27] <= 9'b101001001; // bankl $b, $0
memory[28] <= 9'b011001001; // addi $b, 1
memory[29] <= 9'b101011111; // bankl $d, $3
memory[30] <= 9'b001011010; // sb $d, $b
memory[31] <= 9'b011001001; // addi $b, 1
memory[32] <= 9'b001010010; // sb $c, $b
memory[33] <= 9'b010001000; // zero $b
memory[34] <= 9'b011001001; // addi $b, 1
memory[35] <= 9'b101001010; // banks $b, $1
memory[36] <= 9'b101111100; // jb Inc
// Check to see if any swaps have been made in the last iteration
// SwapChk:
memory[37] <= 9'b101001011; // bankl $b, $1
memory[38] <= 9'b110001001; // beq $b, JE
memory[39] <= 9'b100100001; // jf Reset
// JE:
memory[40] <= 9'b100100011; // jf End
// Reset:
memory[41] <= 9'b010001000; // zero $b
memory[42] <= 9'b101001000; // banks $b, $0
memory[43] <= 9'b101111011; // jb LoadNext
// End:
memory[44] <= 9'b000000000; // halt
// Binary Search