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This commit is contained in:
Johannes
2019-04-06 17:54:50 -04:00
parent e6cb8e536b e937485bd4
commit 616dac4d29
31 changed files with 899 additions and 525 deletions
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629
CPU9bits_tb_behav.wcfg
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@@ -11,241 +11,514 @@
</db_ref> </db_ref>
</db_ref_list> </db_ref_list>
<zoom_setting> <zoom_setting>
<ZoomStartTime time="179098989fs"></ZoomStartTime> <ZoomStartTime time="27136463050fs"></ZoomStartTime>
<ZoomEndTime time="282180203fs"></ZoomEndTime> <ZoomEndTime time="54578707391fs"></ZoomEndTime>
<Cursor1Time time="265000000fs"></Cursor1Time> <Cursor1Time time="50005000000fs"></Cursor1Time>
</zoom_setting> </zoom_setting>
<column_width_setting> <column_width_setting>
<NameColumnWidth column_width="188"></NameColumnWidth> <NameColumnWidth column_width="188"></NameColumnWidth>
<ValueColumnWidth column_width="96"></ValueColumnWidth> <ValueColumnWidth column_width="84"></ValueColumnWidth>
</column_width_setting> </column_width_setting>
<WVObjectSize size="11" /> <WVObjectSize size="9" />
<wvobject fp_name="/CPU9bits_tb/clk" type="logic"> <wvobject fp_name="group1143" type="group">
<obj_property name="ElementShortName">clk</obj_property> <obj_property name="label">CPU</obj_property>
<obj_property name="ObjectShortName">clk</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/reset" type="logic">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/clk" type="logic">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/result" type="array">
<obj_property name="ElementShortName">result[8:0]</obj_property>
<obj_property name="ObjectShortName">result[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/done" type="logic">
<obj_property name="ElementShortName">done</obj_property>
<obj_property name="ObjectShortName">done</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/instr" type="array">
<obj_property name="ElementShortName">instr[8:0]</obj_property>
<obj_property name="ObjectShortName">instr[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/op1" type="array">
<obj_property name="ElementShortName">op1[8:0]</obj_property>
<obj_property name="ObjectShortName">op1[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/op0" type="array">
<obj_property name="ElementShortName">op0[8:0]</obj_property>
<obj_property name="ObjectShortName">op0[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FUAddr" type="array">
<obj_property name="ElementShortName">FUAddr[8:0]</obj_property>
<obj_property name="ObjectShortName">FUAddr[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FUJB" type="array">
<obj_property name="ElementShortName">FUJB[8:0]</obj_property>
<obj_property name="ObjectShortName">FUJB[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/PCout" type="array">
<obj_property name="ElementShortName">PCout[8:0]</obj_property>
<obj_property name="ObjectShortName">PCout[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/JBRes" type="array">
<obj_property name="ElementShortName">JBRes[8:0]</obj_property>
<obj_property name="ObjectShortName">JBRes[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FUJ" type="array">
<obj_property name="ElementShortName">FUJ[8:0]</obj_property>
<obj_property name="ObjectShortName">FUJ[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FUB" type="array">
<obj_property name="ElementShortName">FUB[8:0]</obj_property>
<obj_property name="ObjectShortName">FUB[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/AddiOut" type="array">
<obj_property name="ElementShortName">AddiOut[8:0]</obj_property>
<obj_property name="ObjectShortName">AddiOut[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/AluOut" type="array">
<obj_property name="ElementShortName">AluOut[8:0]</obj_property>
<obj_property name="ObjectShortName">AluOut[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RFIn" type="array">
<obj_property name="ElementShortName">RFIn[8:0]</obj_property>
<obj_property name="ObjectShortName">RFIn[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/loadMux" type="array">
<obj_property name="ElementShortName">loadMux[8:0]</obj_property>
<obj_property name="ObjectShortName">loadMux[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dataMemOut" type="array">
<obj_property name="ElementShortName">dataMemOut[8:0]</obj_property>
<obj_property name="ObjectShortName">dataMemOut[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/linkData" type="array">
<obj_property name="ElementShortName">linkData[8:0]</obj_property>
<obj_property name="ObjectShortName">linkData[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/SE1N" type="array">
<obj_property name="ElementShortName">SE1N[8:0]</obj_property>
<obj_property name="ObjectShortName">SE1N[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/SE2N" type="array">
<obj_property name="ElementShortName">SE2N[8:0]</obj_property>
<obj_property name="ObjectShortName">SE2N[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/SE3N" type="array">
<obj_property name="ElementShortName">SE3N[8:0]</obj_property>
<obj_property name="ObjectShortName">SE3N[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/bankData" type="array">
<obj_property name="ElementShortName">bankData[8:0]</obj_property>
<obj_property name="ObjectShortName">bankData[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/bankOP" type="array">
<obj_property name="ElementShortName">bankOP[8:0]</obj_property>
<obj_property name="ObjectShortName">bankOP[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/jumpNeg" type="array">
<obj_property name="ElementShortName">jumpNeg[8:0]</obj_property>
<obj_property name="ObjectShortName">jumpNeg[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/aluOp" type="array">
<obj_property name="ElementShortName">aluOp[3:0]</obj_property>
<obj_property name="ObjectShortName">aluOp[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FU" type="array">
<obj_property name="ElementShortName">FU[2:0]</obj_property>
<obj_property name="ObjectShortName">FU[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/bankS" type="array">
<obj_property name="ElementShortName">bankS[1:0]</obj_property>
<obj_property name="ObjectShortName">bankS[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/addiS" type="logic">
<obj_property name="ElementShortName">addiS</obj_property>
<obj_property name="ObjectShortName">addiS</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RegEn" type="logic">
<obj_property name="ElementShortName">RegEn</obj_property>
<obj_property name="ObjectShortName">RegEn</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/loadS" type="logic">
<obj_property name="ElementShortName">loadS</obj_property>
<obj_property name="ObjectShortName">loadS</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/fetchBranch" type="logic">
<obj_property name="ElementShortName">fetchBranch</obj_property>
<obj_property name="ObjectShortName">fetchBranch</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/halt" type="logic">
<obj_property name="ElementShortName">halt</obj_property>
<obj_property name="ObjectShortName">halt</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/cout0" type="logic">
<obj_property name="ElementShortName">cout0</obj_property>
<obj_property name="ObjectShortName">cout0</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/cout1" type="logic">
<obj_property name="ElementShortName">cout1</obj_property>
<obj_property name="ObjectShortName">cout1</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/link" type="logic">
<obj_property name="ElementShortName">link</obj_property>
<obj_property name="ObjectShortName">link</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/js" type="logic">
<obj_property name="ElementShortName">js</obj_property>
<obj_property name="ObjectShortName">js</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dataMemEn" type="logic">
<obj_property name="ElementShortName">dataMemEn</obj_property>
<obj_property name="ObjectShortName">dataMemEn</obj_property>
</wvobject>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/reset" type="logic"> <wvobject fp_name="group1104" type="group">
<obj_property name="ElementShortName">reset</obj_property> <obj_property name="label">Control Unit</obj_property>
<obj_property name="ObjectShortName">reset</obj_property> <obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/CU/instIn" type="array">
<obj_property name="ElementShortName">instIn[3:0]</obj_property>
<obj_property name="ObjectShortName">instIn[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/CU/functBit" type="logic">
<obj_property name="ElementShortName">functBit</obj_property>
<obj_property name="ObjectShortName">functBit</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/CU/aluOut" type="array">
<obj_property name="ElementShortName">aluOut[3:0]</obj_property>
<obj_property name="ObjectShortName">aluOut[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/CU/FU" type="array">
<obj_property name="ElementShortName">FU[2:0]</obj_property>
<obj_property name="ObjectShortName">FU[2:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/CU/bank" type="array">
<obj_property name="ElementShortName">bank[1:0]</obj_property>
<obj_property name="ObjectShortName">bank[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/CU/addi" type="logic">
<obj_property name="ElementShortName">addi</obj_property>
<obj_property name="ObjectShortName">addi</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/CU/mem" type="logic">
<obj_property name="ElementShortName">mem</obj_property>
<obj_property name="ObjectShortName">mem</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/CU/dataMemEn" type="logic">
<obj_property name="ElementShortName">dataMemEn</obj_property>
<obj_property name="ObjectShortName">dataMemEn</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/CU/RegEn" type="logic">
<obj_property name="ElementShortName">RegEn</obj_property>
<obj_property name="ObjectShortName">RegEn</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/CU/halt" type="logic">
<obj_property name="ElementShortName">halt</obj_property>
<obj_property name="ObjectShortName">halt</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/CU/link" type="logic">
<obj_property name="ElementShortName">link</obj_property>
<obj_property name="ObjectShortName">link</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/CU/js" type="logic">
<obj_property name="ElementShortName">js</obj_property>
<obj_property name="ObjectShortName">js</obj_property>
</wvobject>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/done" type="logic"> <wvobject fp_name="group1069" type="group">
<obj_property name="ElementShortName">done</obj_property> <obj_property name="label">Fetch Unit</obj_property>
<obj_property name="ObjectShortName">done</obj_property> <obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/clk" type="logic">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/reset" type="logic">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/op_idx" type="logic">
<obj_property name="ElementShortName">op_idx</obj_property>
<obj_property name="ObjectShortName">op_idx</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/AddrIn" type="array">
<obj_property name="ElementShortName">AddrIn[8:0]</obj_property>
<obj_property name="ObjectShortName">AddrIn[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/AddrOut" type="array">
<obj_property name="ElementShortName">AddrOut[8:0]</obj_property>
<obj_property name="ObjectShortName">AddrOut[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/progC_out" type="array">
<obj_property name="ElementShortName">progC_out[8:0]</obj_property>
<obj_property name="ObjectShortName">progC_out[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/result_m" type="array">
<obj_property name="ElementShortName">result_m[8:0]</obj_property>
<obj_property name="ObjectShortName">result_m[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/cout" type="logic">
<obj_property name="ElementShortName">cout</obj_property>
<obj_property name="ObjectShortName">cout</obj_property>
</wvobject>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/instr" type="array"> <wvobject fp_name="group1091" type="group">
<obj_property name="ElementShortName">instr[8:0]</obj_property> <obj_property name="label">ALU</obj_property>
<obj_property name="ObjectShortName">instr[8:0]</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="Radix">BINARYRADIX</obj_property> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/opcode" type="array">
<obj_property name="ElementShortName">opcode[3:0]</obj_property>
<obj_property name="ObjectShortName">opcode[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/operand0" type="array">
<obj_property name="ElementShortName">operand0[8:0]</obj_property>
<obj_property name="ObjectShortName">operand0[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/operand1" type="array">
<obj_property name="ElementShortName">operand1[8:0]</obj_property>
<obj_property name="ObjectShortName">operand1[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result" type="array">
<obj_property name="ElementShortName">result[8:0]</obj_property>
<obj_property name="ObjectShortName">result[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_A" type="array">
<obj_property name="ElementShortName">result_A[8:0]</obj_property>
<obj_property name="ObjectShortName">result_A[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_B" type="array">
<obj_property name="ElementShortName">result_B[8:0]</obj_property>
<obj_property name="ObjectShortName">result_B[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_C" type="array">
<obj_property name="ElementShortName">result_C[8:0]</obj_property>
<obj_property name="ObjectShortName">result_C[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_D" type="array">
<obj_property name="ElementShortName">result_D[8:0]</obj_property>
<obj_property name="ObjectShortName">result_D[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_E" type="array">
<obj_property name="ElementShortName">result_E[8:0]</obj_property>
<obj_property name="ObjectShortName">result_E[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_F" type="array">
<obj_property name="ElementShortName">result_F[8:0]</obj_property>
<obj_property name="ObjectShortName">result_F[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_G" type="array">
<obj_property name="ElementShortName">result_G[8:0]</obj_property>
<obj_property name="ObjectShortName">result_G[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_H" type="array">
<obj_property name="ElementShortName">result_H[8:0]</obj_property>
<obj_property name="ObjectShortName">result_H[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_I" type="array">
<obj_property name="ElementShortName">result_I[8:0]</obj_property>
<obj_property name="ObjectShortName">result_I[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_J" type="array">
<obj_property name="ElementShortName">result_J[8:0]</obj_property>
<obj_property name="ObjectShortName">result_J[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_K" type="array">
<obj_property name="ElementShortName">result_K[8:0]</obj_property>
<obj_property name="ObjectShortName">result_K[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_L" type="array">
<obj_property name="ElementShortName">result_L[8:0]</obj_property>
<obj_property name="ObjectShortName">result_L[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_M" type="array">
<obj_property name="ElementShortName">result_M[8:0]</obj_property>
<obj_property name="ObjectShortName">result_M[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_N" type="array">
<obj_property name="ElementShortName">result_N[8:0]</obj_property>
<obj_property name="ObjectShortName">result_N[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_O" type="array">
<obj_property name="ElementShortName">result_O[8:0]</obj_property>
<obj_property name="ObjectShortName">result_O[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/result_P" type="array">
<obj_property name="ElementShortName">result_P[8:0]</obj_property>
<obj_property name="ObjectShortName">result_P[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/alu/cout" type="logic">
<obj_property name="ElementShortName">cout</obj_property>
<obj_property name="ObjectShortName">cout</obj_property>
</wvobject>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/AddrOut" type="array"> <wvobject fp_name="group902" type="group">
<obj_property name="ElementShortName">AddrOut[8:0]</obj_property>
<obj_property name="ObjectShortName">AddrOut[8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="group429" type="group">
<obj_property name="label">Registers</obj_property> <obj_property name="label">Registers</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/clk" type="logic">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/reset" type="logic">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/enable" type="logic">
<obj_property name="ElementShortName">enable</obj_property>
<obj_property name="ObjectShortName">enable</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/write_index" type="array">
<obj_property name="ElementShortName">write_index[1:0]</obj_property>
<obj_property name="ObjectShortName">write_index[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/op0_idx" type="array">
<obj_property name="ElementShortName">op0_idx[1:0]</obj_property>
<obj_property name="ObjectShortName">op0_idx[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/op1_idx" type="array">
<obj_property name="ElementShortName">op1_idx[1:0]</obj_property>
<obj_property name="ObjectShortName">op1_idx[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/write_data" type="array">
<obj_property name="ElementShortName">write_data[8:0]</obj_property>
<obj_property name="ObjectShortName">write_data[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/op0" type="array">
<obj_property name="ElementShortName">op0[8:0]</obj_property>
<obj_property name="ObjectShortName">op0[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/op1" type="array">
<obj_property name="ElementShortName">op1[8:0]</obj_property>
<obj_property name="ObjectShortName">op1[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/decOut" type="array">
<obj_property name="ElementShortName">decOut[3:0]</obj_property>
<obj_property name="ObjectShortName">decOut[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r0_out" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r0_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r0_out[8:0]</obj_property> <obj_property name="ElementShortName">r0_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r0_out[8:0]</obj_property> <obj_property name="ObjectShortName">r0_out[8:0]</obj_property>
<obj_property name="label">RegisterA</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r1_out" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r1_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r1_out[8:0]</obj_property> <obj_property name="ElementShortName">r1_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r1_out[8:0]</obj_property> <obj_property name="ObjectShortName">r1_out[8:0]</obj_property>
<obj_property name="label">RegisterB</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r2_out" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r2_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r2_out[8:0]</obj_property> <obj_property name="ElementShortName">r2_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r2_out[8:0]</obj_property> <obj_property name="ObjectShortName">r2_out[8:0]</obj_property>
<obj_property name="label">RegisterC</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r3_out" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/RF/r3_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r3_out[8:0]</obj_property> <obj_property name="ElementShortName">r3_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r3_out[8:0]</obj_property> <obj_property name="ObjectShortName">r3_out[8:0]</obj_property>
<obj_property name="label">RegisterD</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
</wvobject> </wvobject>
<wvobject fp_name="group430" type="group"> <wvobject fp_name="group917" type="group">
<obj_property name="label">Banks</obj_property> <obj_property name="label">Banks</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/clk" type="logic">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/reset" type="logic">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/enable" type="logic">
<obj_property name="ElementShortName">enable</obj_property>
<obj_property name="ObjectShortName">enable</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/write_index" type="array">
<obj_property name="ElementShortName">write_index[1:0]</obj_property>
<obj_property name="ObjectShortName">write_index[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/op0_idx" type="array">
<obj_property name="ElementShortName">op0_idx[1:0]</obj_property>
<obj_property name="ObjectShortName">op0_idx[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/op1_idx" type="array">
<obj_property name="ElementShortName">op1_idx[1:0]</obj_property>
<obj_property name="ObjectShortName">op1_idx[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/write_data" type="array">
<obj_property name="ElementShortName">write_data[8:0]</obj_property>
<obj_property name="ObjectShortName">write_data[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/op0" type="array">
<obj_property name="ElementShortName">op0[8:0]</obj_property>
<obj_property name="ObjectShortName">op0[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/op1" type="array">
<obj_property name="ElementShortName">op1[8:0]</obj_property>
<obj_property name="ObjectShortName">op1[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/decOut" type="array">
<obj_property name="ElementShortName">decOut[3:0]</obj_property>
<obj_property name="ObjectShortName">decOut[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r0_out" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r0_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r0_out[8:0]</obj_property> <obj_property name="ElementShortName">r0_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r0_out[8:0]</obj_property> <obj_property name="ObjectShortName">r0_out[8:0]</obj_property>
<obj_property name="label">Bank0</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r1_out" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r1_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r1_out[8:0]</obj_property> <obj_property name="ElementShortName">r1_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r1_out[8:0]</obj_property> <obj_property name="ObjectShortName">r1_out[8:0]</obj_property>
<obj_property name="label">Bank1</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r2_out" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r2_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r2_out[8:0]</obj_property> <obj_property name="ElementShortName">r2_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r2_out[8:0]</obj_property> <obj_property name="ObjectShortName">r2_out[8:0]</obj_property>
<obj_property name="label">Bank2</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r3_out" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/Bank/r3_out" type="array">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">r3_out[8:0]</obj_property> <obj_property name="ElementShortName">r3_out[8:0]</obj_property>
<obj_property name="ObjectShortName">r3_out[8:0]</obj_property> <obj_property name="ObjectShortName">r3_out[8:0]</obj_property>
<obj_property name="label">Bank3</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
</wvobject> </wvobject>
<wvobject type="divider" fp_name="divider431"> <wvobject type="divider" fp_name="divider431">
<obj_property name="label">Divider</obj_property> <obj_property name="label">Divider</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory" type="array"> <wvobject fp_name="group921" type="group">
<obj_property name="label">Instruction Memory</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">memory[23:0][8:0]</obj_property> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/iM/address" type="array">
<obj_property name="ObjectShortName">memory[23:0][8:0]</obj_property> <obj_property name="ElementShortName">address[8:0]</obj_property>
<obj_property name="ObjectShortName">address[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/iM/memory" type="array">
<obj_property name="ElementShortName">memory[100:0][8:0]</obj_property>
<obj_property name="ObjectShortName">memory[100:0][8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/iM/readData" type="array">
<obj_property name="ElementShortName">readData[8:0]</obj_property>
<obj_property name="ObjectShortName">readData[8:0]</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="group928" type="group">
<obj_property name="label">Data Memory</obj_property> <obj_property name="label">Data Memory</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/clk" type="logic">
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[23]" type="array"> <obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ElementShortName">[23][8:0]</obj_property> <obj_property name="ObjectShortName">clk</obj_property>
<obj_property name="ObjectShortName">[23][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[22]" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/writeEnable" type="logic">
<obj_property name="ElementShortName">[22][8:0]</obj_property> <obj_property name="ElementShortName">writeEnable</obj_property>
<obj_property name="ObjectShortName">[22][8:0]</obj_property> <obj_property name="ObjectShortName">writeEnable</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[21]" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/address" type="array">
<obj_property name="ElementShortName">[21][8:0]</obj_property> <obj_property name="ElementShortName">address[8:0]</obj_property>
<obj_property name="ObjectShortName">[21][8:0]</obj_property> <obj_property name="ObjectShortName">address[8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[20]" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/writeData" type="array">
<obj_property name="ElementShortName">[20][8:0]</obj_property> <obj_property name="ElementShortName">writeData[8:0]</obj_property>
<obj_property name="ObjectShortName">[20][8:0]</obj_property> <obj_property name="ObjectShortName">writeData[8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[19]" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/readData" type="array">
<obj_property name="ElementShortName">[19][8:0]</obj_property> <obj_property name="ElementShortName">readData[8:0]</obj_property>
<obj_property name="ObjectShortName">[19][8:0]</obj_property> <obj_property name="ObjectShortName">readData[8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[18]" type="array"> <wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory" type="array">
<obj_property name="ElementShortName">[18][8:0]</obj_property> <obj_property name="ElementShortName">memory[100:0][8:0]</obj_property>
<obj_property name="ObjectShortName">[18][8:0]</obj_property> <obj_property name="ObjectShortName">memory[100:0][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[17]" type="array">
<obj_property name="ElementShortName">[17][8:0]</obj_property>
<obj_property name="ObjectShortName">[17][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[16]" type="array">
<obj_property name="ElementShortName">[16][8:0]</obj_property>
<obj_property name="ObjectShortName">[16][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[15]" type="array">
<obj_property name="ElementShortName">[15][8:0]</obj_property>
<obj_property name="ObjectShortName">[15][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[14]" type="array">
<obj_property name="ElementShortName">[14][8:0]</obj_property>
<obj_property name="ObjectShortName">[14][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[13]" type="array">
<obj_property name="ElementShortName">[13][8:0]</obj_property>
<obj_property name="ObjectShortName">[13][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[12]" type="array">
<obj_property name="ElementShortName">[12][8:0]</obj_property>
<obj_property name="ObjectShortName">[12][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[11]" type="array">
<obj_property name="ElementShortName">[11][8:0]</obj_property>
<obj_property name="ObjectShortName">[11][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[10]" type="array">
<obj_property name="ElementShortName">[10][8:0]</obj_property>
<obj_property name="ObjectShortName">[10][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[9]" type="array">
<obj_property name="ElementShortName">[9][8:0]</obj_property>
<obj_property name="ObjectShortName">[9][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[8]" type="array">
<obj_property name="ElementShortName">[8][8:0]</obj_property>
<obj_property name="ObjectShortName">[8][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[7]" type="array">
<obj_property name="ElementShortName">[7][8:0]</obj_property>
<obj_property name="ObjectShortName">[7][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[6]" type="array">
<obj_property name="ElementShortName">[6][8:0]</obj_property>
<obj_property name="ObjectShortName">[6][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[5]" type="array">
<obj_property name="ElementShortName">[5][8:0]</obj_property>
<obj_property name="ObjectShortName">[5][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[4]" type="array">
<obj_property name="ElementShortName">[4][8:0]</obj_property>
<obj_property name="ObjectShortName">[4][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[3]" type="array">
<obj_property name="ElementShortName">[3][8:0]</obj_property>
<obj_property name="ObjectShortName">[3][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[2]" type="array">
<obj_property name="ElementShortName">[2][8:0]</obj_property>
<obj_property name="ObjectShortName">[2][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[1]" type="array">
<obj_property name="ElementShortName">[1][8:0]</obj_property>
<obj_property name="ObjectShortName">[1][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/memory[0]" type="array">
<obj_property name="ElementShortName">[0][8:0]</obj_property>
<obj_property name="ObjectShortName">[0][8:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/dM/readData" type="array">
<obj_property name="ElementShortName">readData[8:0]</obj_property>
<obj_property name="ObjectShortName">readData[8:0]</obj_property>
</wvobject>
<wvobject fp_name="/CPU9bits_tb/CPU9bits0/FetchU/AddrIn" type="array">
<obj_property name="ElementShortName">AddrIn[8:0]</obj_property>
<obj_property name="ObjectShortName">AddrIn[8:0]</obj_property>
</wvobject> </wvobject>
</wave_config> </wave_config>

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lab2CA.runs/.jobs/vrs_config_59.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_60.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_61.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_62.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_63.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_64.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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lab2CA.runs/.jobs/vrs_config_65.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

8
lab2CA.runs/.jobs/vrs_config_66.xml Normal file
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

8
lab2CA.runs/.jobs/vrs_config_67.xml Normal file
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

8
lab2CA.runs/.jobs/vrs_config_68.xml Normal file
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

8
lab2CA.runs/.jobs/vrs_config_69.xml Normal file
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

8
lab2CA.runs/.jobs/vrs_config_70.xml Normal file
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

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2
lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.pb
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@@ -1,2 +0,0 @@
2012.4<EFBFBD>)Timing analysis from Implemented netlist.

9
lab2CA.runs/impl_1/htr.txt
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@@ -1,9 +0,0 @@
REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
REM
vivado -log CPU9bits.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace

BIN
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0
lab2CA.runs/synth_1/CPU9bits.tcl → lab2CA.runs/synth_1/CPU9bits_tb.tcl
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0
lab2CA.runs/synth_1/CPU9bits.vds → lab2CA.runs/synth_1/CPU9bits_tb.vds
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0
lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt → lab2CA.runs/synth_1/CPU9bits_tb_utilization_synth.rpt
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2
lab2CA.runs/synth_1/htr.txt
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@@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status.
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
REM REM
vivado -log CPU9bits.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl vivado -log CPU9bits_tb.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl

6
lab2CA.sim/sim_1/behav/xsim/webtalk_26660.backup.jou → lab2CA.sim/sim_1/behav/xsim/webtalk_10700.backup.jou
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@@ -2,10 +2,10 @@
# Webtalk v2018.3 (64-bit) # Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Mar 29 15:21:59 2019 # Start of session at: Sat Apr 6 13:17:03 2019
# Process ID: 26660 # Process ID: 10700
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou # Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#----------------------------------------------------------- #-----------------------------------------------------------

12
lab2CA.sim/sim_1/behav/xsim/webtalk_11564.backup.jou Normal file
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@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Apr 6 13:16:30 2019
# Process ID: 11564
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/REPOSITORIES/Educational/Western -notrace

4
lab2CA.sim/sim_1/behav/xsim/webtalk_14652.backup.jou → lab2CA.sim/sim_1/behav/xsim/webtalk_16352.backup.jou
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@@ -2,8 +2,8 @@
# Webtalk v2018.3 (64-bit) # Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Mar 29 15:13:54 2019 # Start of session at: Sat Apr 6 14:28:59 2019
# Process ID: 14652 # Process ID: 16352
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log

306
lab2CA.srcs/sources_1/new/ControlUnit.v
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@@ -13,71 +13,72 @@ module ControlUnit(
case(instIn) case(instIn)
4'b0000: // Halt/NOP 4'b0000: // Halt/NOP
begin begin
halt <= 1'b1; halt <= 1'b1;
RegEn <= 1'b1; RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
addi <= 1'b0; addi <= 1'b0;
dataMemEn <= 1'b0; // Disabled dataMemEn <= 1'b0; // Disabled
aluOut <= 4'b0000; aluOut <= 4'b0000;
mem <= 1'b0; mem <= 1'b0;
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
4'b0001: // Load Byte 4'b0001: // Load Byte
begin begin
aluOut <= 4'b0000; aluOut <= 4'b0000;
mem <= 1'b1; mem <= 1'b1;
dataMemEn <= 1'b0; // Disabled dataMemEn <= 1'b0; // Disabled
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
addi <= 1'b0; addi <= 1'b0;
halt <= 1'b0; halt <= 1'b0;
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
4'b0010: // Store Byte 4'b0010: // Store Byte
begin begin
aluOut <= 4'b0000; aluOut <= 4'b0000;
mem <= 1'b0; mem <= 1'b0;
dataMemEn <= 1'b1; // Enabled dataMemEn <= 1'b1; // Enabled
RegEn <= 1'b1; RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
halt <= 1'b0; halt <= 1'b0;
addi <= 1'b0; addi <= 1'b0;
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
4'b0011: // Link 4'b0011: // Link
begin begin
halt <= 1'b0; halt <= 1'b0;
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; FU <= 3'b001;
addi <= 1'b0; addi <= 1'b0;
aluOut <= 4'b0000; aluOut <= 4'b0000;
mem <= 1'b0; mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled dataMemEn <= 1'b0; // Disabled
link <= 1'b1; link <= 1'b1;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
4'b0100: // Zero 4'b0100: // Zero
begin begin
aluOut <= 4'b1011; aluOut <= 4'b1011;
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
halt <= 1'b0; halt <= 1'b0;
addi <= 1'b0; addi <= 1'b0;
mem <= 1'b0; mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled dataMemEn <= 1'b0; // Disabled
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
4'b0101: // Add/Subtract 4'b0101: // Add/Subtract
if(functBit == 1) begin // Subtract if(functBit == 1) // Subtract
begin
aluOut <= 4'b0001; aluOut <= 4'b0001;
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; FU <= 3'b001;
@@ -88,8 +89,9 @@ module ControlUnit(
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
else begin // Add else // Add
begin
aluOut <= 4'b0000; aluOut <= 4'b0000;
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
@@ -100,114 +102,114 @@ module ControlUnit(
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
4'b0110: // Add Immediate 4'b0110: // Add Immediate
begin begin
aluOut <= 4'b1010; aluOut <= 4'b1010;
addi <= 1'b1; addi <= 1'b1;
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
halt <= 1'b0; halt <= 1'b0;
mem <= 1'b0; mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled dataMemEn <= 1'b0; // Disabled
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
4'b0111: // Set if Less Than 4'b0111: // Set if Less Than
begin begin
aluOut <= 4'b1001; aluOut <= 4'b1001;
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
halt <= 1'b0; halt <= 1'b0;
addi <= 1'b0; addi <= 1'b0;
mem <= 1'b0; mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled dataMemEn <= 1'b0; // Disabled
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
4'b1000: // Jump to Register 4'b1000: // Jump to Register
begin begin
aluOut <= 4'b0000; aluOut <= 4'b0000;
FU <= 3'b000; FU <= 3'b000;
RegEn <= 1'b1; RegEn <= 1'b1;
halt <= 1'b0; halt <= 1'b0;
addi <= 1'b0; addi <= 1'b0;
mem <= 1'b0; mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled dataMemEn <= 1'b0; // Disabled
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
4'b1001: // Jump Forward 4'b1001: // Jump Forward
begin begin
aluOut <= 4'b0000; aluOut <= 4'b0000;
FU <= 3'b010; FU <= 3'b010;
RegEn <= 1'b1; RegEn <= 1'b1;
halt <= 1'b0; halt <= 1'b0;
addi <= 1'b0; addi <= 1'b0;
mem <= 1'b0; mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled dataMemEn <= 1'b0; // Disabled
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
4'b1010: // Bank Load/Bank Store 4'b1010: // Bank Load/Bank Store
begin begin
halt <= 1'b0; halt <= 1'b0;
RegEn <= !functBit; RegEn <= !functBit;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
addi <= 1'b0; addi <= 1'b0;
aluOut <= 4'b0000; aluOut <= 4'b0000;
dataMemEn <= 1'b0; // Disabled dataMemEn <= 1'b0; // Disabled
mem <= 1'b0; mem <= 1'b0;
link <= 1'b0; link <= 1'b0;
bank <= {functBit,functBit}; bank <= {functBit,functBit};
js <= 1'b0; js <= 1'b0;
end end
4'b1011: // Jump Backward 4'b1011: // Jump Backward
begin begin
aluOut <= 4'b0000; aluOut <= 4'b0000;
FU <= 3'b010; FU <= 3'b010;
RegEn <= 1'b1; RegEn <= 1'b1;
halt <= 1'b0; halt <= 1'b0;
addi <= 1'b0; addi <= 1'b0;
mem <= 1'b0; mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled dataMemEn <= 1'b0; // Disabled
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b1; js <= 1'b1;
end end
4'b1100: // Branch if Zero 4'b1100: // Branch if Zero
begin begin
aluOut <= 4'b1010; aluOut <= 4'b1010;
FU <= 3'b110; FU <= 3'b110;
RegEn <= 1'b1; RegEn <= 1'b1;
halt <= 1'b0; halt <= 1'b0;
addi <= 1'b0; addi <= 1'b0;
mem <= 1'b0; mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled dataMemEn <= 1'b0; // Disabled
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
4'b1101: // NOR 4'b1101: // NOR
begin begin
aluOut <= 4'b0011; aluOut <= 4'b0011;
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
halt <= 1'b0; halt <= 1'b0;
addi <= 1'b0; addi <= 1'b0;
mem <= 1'b0; mem <= 1'b0;
dataMemEn <= 1'b0; // Disabled dataMemEn <= 1'b0; // Disabled
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
4'b1110: // OR/AND 4'b1110: // OR/AND
if(functBit == 1) // AND if(functBit == 1) // AND
begin begin
aluOut <= 4'b0100; aluOut <= 4'b0100;
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
@@ -218,9 +220,9 @@ module ControlUnit(
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
else // OR else // OR
begin begin
aluOut <= 4'b0010; aluOut <= 4'b0010;
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
@@ -231,10 +233,10 @@ module ControlUnit(
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
4'b1111: // Shift Right Logical/Shift Left Logical 4'b1111: // Shift Right Logical/Shift Left Logical
if(functBit == 1) // Shift Right Logical if(functBit == 1) // Shift Right Logical
begin begin
aluOut <= 4'b0110; aluOut <= 4'b0110;
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
@@ -245,9 +247,9 @@ module ControlUnit(
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
else // Shift Left Logical else // Shift Left Logical
begin begin
aluOut <= 4'b0101; aluOut <= 4'b0101;
RegEn <= 1'b0; RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching FU <= 3'b001; // Disable Branching
@@ -258,19 +260,19 @@ module ControlUnit(
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
default: default:
begin begin
halt <= 1'b1; halt <= 1'b1;
RegEn <= 1'b1; RegEn <= 1'b1;
FU <= 3'b001; FU <= 3'b001;
dataMemEn <= 1'b0; // Disabled dataMemEn <= 1'b0; // Disabled
addi <= 1'b0; addi <= 1'b0;
aluOut <= 4'b0000; aluOut <= 4'b0000;
mem <= 1'b0; mem <= 1'b0;
link <= 1'b0; link <= 1'b0;
bank <= 2'b10; bank <= 2'b10;
js <= 1'b0; js <= 1'b0;
end end
endcase endcase
end end

11
lab2CA.srcs/sources_1/new/FetchUnit.v
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@@ -1,9 +1,11 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module FetchUnit(input wire clk, reset, module FetchUnit(
input wire op_idx, input wire clk, reset,
input wire [8:0] AddrIn, input wire op_idx,
output wire [8:0] AddrOut); input wire [8:0] AddrIn,
output wire [8:0] AddrOut
);
//Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a) //Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a)
wire [8:0] progC_out, result_m; wire [8:0] progC_out, result_m;
@@ -29,7 +31,6 @@ module FetchUnit(input wire clk, reset,
.out(result_m), .out(result_m),
.switch(op_idx)); .switch(op_idx));
endmodule endmodule
//testbench //testbench

204
lab2CA.srcs/sources_1/new/dataMemory.v
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@@ -6,7 +6,7 @@ module dataMemory(
output reg [8:0] readData output reg [8:0] readData
); );
reg [8:0] memory [512:0]; // Maximum of 512 memory locations reg [8:0] memory [100:0]; // Maximum of 512 memory locations
// Vivado will give warnings of unconnected ports on the "address" bus if they are unused // Vivado will give warnings of unconnected ports on the "address" bus if they are unused
initial begin initial begin
@@ -97,107 +97,107 @@ module dataMemory(
// Program 1 Test Data // Program 1 Test Data
// memory[0] <= 9'd100; memory[0] <= 9'd100;
// memory[1] <= 9'd58; memory[1] <= 9'd58;
// memory[2] <= 9'd6; memory[2] <= 9'd6;
// memory[3] <= 9'd12; memory[3] <= 9'd12;
// memory[4] <= 9'b110110000; // -80 memory[4] <= 9'b110110000; // -80
// memory[5] <= 9'd17; memory[5] <= 9'd17;
// memory[6] <= 9'b111011011; // -37 memory[6] <= 9'b111011011; // -37
// memory[7] <= 9'd25; memory[7] <= 9'd25;
// memory[8] <= -9'd83; // -83 memory[8] <= -9'd83; // -83
// memory[9] <= -9'd98; // -98 memory[9] <= -9'd98; // -98
// memory[10] <= -9'd98; // -98 memory[10] <= -9'd98; // -98
// memory[11] <= -9'd74; // -74 memory[11] <= -9'd74; // -74
// memory[12] <= 9'd70; memory[12] <= 9'd70;
// memory[13] <= -9'd38; // -38 memory[13] <= -9'd38; // -38
// memory[14] <= 9'd52; memory[14] <= 9'd52;
// memory[15] <= -9'd96; // -96 memory[15] <= -9'd96; // -96
// memory[16] <= -9'd32; // -32 memory[16] <= -9'd32; // -32
// memory[17] <= -9'd93; // -93 memory[17] <= -9'd93; // -93
// memory[18] <= -9'd40; // -40 memory[18] <= -9'd40; // -40
// memory[19] <= 9'd59; memory[19] <= 9'd59;
// memory[20] <= 9'd10; memory[20] <= 9'd10;
// memory[21] <= 9'd81; memory[21] <= 9'd81;
// memory[22] <= -9'd23; // -28 memory[22] <= -9'd23; // -28
// memory[23] <=- 9'd99; // -99 memory[23] <=- 9'd99; // -99
// memory[24] <= -9'd41; // -41 memory[24] <= -9'd41; // -41
// memory[25] <= 9'd33; memory[25] <= 9'd33;
// memory[26] <= 9'd98; memory[26] <= 9'd98;
// memory[27] <= 9'd73; memory[27] <= 9'd73;
// memory[28] <= -9'd1; // -1 memory[28] <= -9'd1; // -1
// memory[29] <= 9'd28; memory[29] <= 9'd28;
// memory[30] <= 9'd5; memory[30] <= 9'd5;
// memory[31] <= -9'd74; // -74 memory[31] <= -9'd74; // -74
// memory[32] <= -9'd41; // -41 memory[32] <= -9'd41; // -41
// memory[33] <= 9'd41; memory[33] <= 9'd41;
// memory[34] <= 9'd39; memory[34] <= 9'd39;
// memory[35] <= 9'd62; memory[35] <= 9'd62;
// memory[36] <= 9'd19; memory[36] <= 9'd19;
// memory[37] <= -9'd40; // -40 memory[37] <= -9'd40; // -40
// memory[38] <= -9'd8; // -8 memory[38] <= -9'd8; // -8
// memory[39] <= 9'd92; memory[39] <= 9'd92;
// memory[40] <= 9'd37; memory[40] <= 9'd37;
// memory[41] <= 9'd50; memory[41] <= 9'd50;
// memory[42] <= -9'd72; // -72 memory[42] <= -9'd72; // -72
// memory[43] <= -9'd5; // -5 memory[43] <= -9'd5; // -5
// memory[44] <= 9'd19; memory[44] <= 9'd19;
// memory[45] <= 9'd58; memory[45] <= 9'd58;
// memory[46] <= -9'd13; // -13 memory[46] <= -9'd13; // -13
// memory[47] <= 9'd0; memory[47] <= 9'd0;
// memory[48] <= -9'd97; // -97 memory[48] <= -9'd97; // -97
// memory[49] <= 9'd54; memory[49] <= 9'd54;
// memory[50] <= -9'd17; // -17 memory[50] <= -9'd17; // -17
// memory[51] <= -9'd83; // -83 memory[51] <= -9'd83; // -83
// memory[52] <= 9'd53; memory[52] <= 9'd53;
// memory[53] <= 9'd82; memory[53] <= 9'd82;
// memory[54] <= -9'd94; // -94 memory[54] <= -9'd94; // -94
// memory[55] <= -9'd77; // -77 memory[55] <= -9'd77; // -77
// memory[56] <= -9'd74; // -74 memory[56] <= -9'd74; // -74
// memory[57] <= -9'd52; // -52 memory[57] <= -9'd52; // -52
// memory[58] <= 9'd85; memory[58] <= 9'd85;
// memory[59] <= -9'd65; // -65 memory[59] <= -9'd65; // -65
// memory[60] <= -9'd10; // -10 memory[60] <= -9'd10; // -10
// memory[61] <= -9'd45; // -45 memory[61] <= -9'd45; // -45
// memory[62] <= -9'd92; // -92 memory[62] <= -9'd92; // -92
// memory[63] <= -9'd30; // -30 memory[63] <= -9'd30; // -30
// memory[64] <= 9'd18; memory[64] <= 9'd18;
// memory[65] <= -9'd95; // -95 memory[65] <= -9'd95; // -95
// memory[66] <= -9'd27; // -27 memory[66] <= -9'd27; // -27
// memory[67] <= -9'd74; // -74 memory[67] <= -9'd74; // -74
// memory[68] <= 9'd62; memory[68] <= 9'd62;
// memory[69] <= 9'd64; memory[69] <= 9'd64;
// memory[70] <= -9'd9; // -9 memory[70] <= -9'd9; // -9
// memory[71] <= 9'd66; memory[71] <= 9'd66;
// memory[72] <= -9'd71; // -71 memory[72] <= -9'd71; // -71
// memory[73] <= -9'd31; // -31 memory[73] <= -9'd31; // -31
// memory[74] <= 9'd34; memory[74] <= 9'd34;
// memory[75] <= 9'd12; memory[75] <= 9'd12;
// memory[76] <= 9'd3; memory[76] <= 9'd3;
// memory[77] <= 9'd82; memory[77] <= 9'd82;
// memory[78] <= 9'd13; memory[78] <= 9'd13;
// memory[79] <= -9'd78; // -78 memory[79] <= -9'd78; // -78
// memory[80] <= -9'd8; // -8 memory[80] <= -9'd8; // -8
// memory[81] <= 9'd88; memory[81] <= 9'd88;
// memory[82] <= 9'd42; memory[82] <= 9'd42;
// memory[83] <= 9'd42; memory[83] <= 9'd42;
// memory[84] <= 9'd21; memory[84] <= 9'd21;
// memory[85] <= -9'd44; // -44 memory[85] <= -9'd44; // -44
// memory[86] <= 9'd30; memory[86] <= 9'd30;
// memory[87] <= -9'd93; // -93 memory[87] <= -9'd93; // -93
// memory[88] <= 9'd2; memory[88] <= 9'd2;
// memory[89] <= -9'd34; // -34 memory[89] <= -9'd34; // -34
// memory[90] <= 9'd92; memory[90] <= 9'd92;
// memory[91] <= -9'd45; // -45 memory[91] <= -9'd45; // -45
// memory[92] <= 9'd26; memory[92] <= 9'd26;
// memory[93] <= -9'd79; // -79 memory[93] <= -9'd79; // -79
// memory[94] <= 9'd43; memory[94] <= 9'd43;
// memory[95] <= -9'd25; // -25 memory[95] <= -9'd25; // -25
// memory[96] <= -9'd24; // -24 memory[96] <= -9'd24; // -24
// memory[97] <= -9'd25; // -25 memory[97] <= -9'd25; // -25
// memory[98] <= -9'd19; // -19 memory[98] <= -9'd19; // -19
// memory[99] <= -9'd49; // -49 memory[99] <= -9'd49; // -49
// memory[100] <= -9'd8; // -8 memory[100] <= -9'd8; // -8

143
lab2CA.srcs/sources_1/new/instructionMemory.v
View File

@@ -5,16 +5,17 @@ module instructionMemory(
output reg [8:0] readData output reg [8:0] readData
); );
reg [8:0] memory [512:0]; reg [8:0] memory [100:0]; // Maximum of 512 memory locations
// Vivado will give warnings of unconnected ports on the "address" bus if they are unused
initial begin initial begin
//Equation Solver // //Equation Solver
memory[0] <= 9'b000000000; // memory[0] <= 9'b000000000;
memory[1] <= 9'b000100000; //load // memory[1] <= 9'b000100000; //load
memory[2] <= 9'b000101000; //load // memory[2] <= 9'b000101000; //load
memory[3] <= 9'b010100010; //add // memory[3] <= 9'b010100010; //add
memory[4] <= 9'b111100000; //shift left // memory[4] <= 9'b111100000; //shift left
memory[5] <= 9'b111100000; //shift left // memory[5] <= 9'b111100000; //shift left
// //Testing all instructions // //Testing all instructions
// memory[6] <= 9'b010100011; //sub // memory[6] <= 9'b010100011; //sub
@@ -75,69 +76,69 @@ module instructionMemory(
// memory[39] <= 9'b000000000; // memory[39] <= 9'b000000000;
// Bubble Sort //Bubble Sort
// memory[0] <= 9'b000000001; // nop memory[0] <= 9'b000000001; // nop
// // Setup // Setup
// memory[1] <= 9'b010000000; // zero $a memory[1] <= 9'b010000000; // zero $a
// memory[2] <= 9'b000100000; // lb $a, $a memory[2] <= 9'b000100000; // lb $a, $a
// memory[3] <= 9'b010001000; // zero $b memory[3] <= 9'b010001000; // zero $b
// memory[4] <= 9'b010010000; // zero $c memory[4] <= 9'b010010000; // zero $c
// memory[5] <= 9'b010011000; // zero $d memory[5] <= 9'b010011000; // zero $d
// memory[6] <= 9'b101001000; // banks $b, $0 memory[6] <= 9'b101001000; // banks $b, $0
// memory[7] <= 9'b101001010; // banks $b, $1 memory[7] <= 9'b101001010; // banks $b, $1
// memory[8] <= 9'b100100011; // jf EndChk memory[8] <= 9'b100100011; // jf EndChk
// // Increment current index to compare next pair of values // Increment current index to compare next pair of values
// // Inc: // Inc:
// memory[9] <= 9'b101001001; // bankl $b, $0 memory[9] <= 9'b101001001; // bankl $b, $0
// memory[10] <= 9'b011001001; // addi $b, 1 memory[10] <= 9'b011001001; // addi $b, 1
// memory[11] <= 9'b101001000; // banks $b, $0 memory[11] <= 9'b101001000; // banks $b, $0
// // Check if at the end of the array // Check if at the end of the array
// // EndChk: // EndChk:
// memory[12] <= 9'b101001001; // bankl $b, $0 memory[12] <= 9'b101001001; // bankl $b, $0
// memory[13] <= 9'b011101000; // slt $b, $a memory[13] <= 9'b011101000; // slt $b, $a
// memory[14] <= 9'b110001001; // beq $b, JSC memory[14] <= 9'b110001001; // beq $b, JSC
// memory[15] <= 9'b100100001; // jf LoadNext memory[15] <= 9'b100100001; // jf LoadNext
// // JSC: // JSC:
// memory[16] <= 9'b100110100; // jf SwapChk memory[16] <= 9'b100110100; // jf SwapChk
// // Load next values for comparison // Load next values for comparison
// // LoadNext: // LoadNext:
// memory[17] <= 9'b101001001; // bankl $b, $0 memory[17] <= 9'b101001001; // bankl $b, $0
// memory[18] <= 9'b011001001; // addi $b, 1 memory[18] <= 9'b011001001; // addi $b, 1
// memory[19] <= 9'b000110010; // lb $c, $b memory[19] <= 9'b000110010; // lb $c, $b
// memory[20] <= 9'b011001001; // addi $b, 1 memory[20] <= 9'b011001001; // addi $b, 1
// memory[21] <= 9'b000111010; // lb $d, $b memory[21] <= 9'b000111010; // lb $d, $b
// // Compare loaded values to see if they need to be swapped // Compare loaded values to see if they need to be swapped
// memory[22] <= 9'b101011110; // banks $d, $3 memory[22] <= 9'b101011110; // banks $d, $3
// memory[23] <= 9'b011111100; // slt $d, $c memory[23] <= 9'b011111100; // slt $d, $c
// memory[24] <= 9'b110011001; // beq $d, JI memory[24] <= 9'b110011001; // beq $d, JI
// memory[25] <= 9'b100100001; // jf Swap memory[25] <= 9'b100100001; // jf Swap
// // JI: // JI:
// memory[26] <= 9'b101110010; // jb Inc memory[26] <= 9'b101110010; // jb Inc
// // Swap values in array // Swap values in array
// // Swap: // Swap:
// memory[27] <= 9'b101001001; // bankl $b, $0 memory[27] <= 9'b101001001; // bankl $b, $0
// memory[28] <= 9'b011001001; // addi $b, 1 memory[28] <= 9'b011001001; // addi $b, 1
// memory[29] <= 9'b101011111; // bankl $d, $3 memory[29] <= 9'b101011111; // bankl $d, $3
// memory[30] <= 9'b001011010; // sb $d, $b memory[30] <= 9'b001011010; // sb $d, $b
// memory[31] <= 9'b011001001; // addi $b, 1 memory[31] <= 9'b011001001; // addi $b, 1
// memory[32] <= 9'b001010010; // sb $c, $b memory[32] <= 9'b001010010; // sb $c, $b
// memory[33] <= 9'b010001000; // zero $b memory[33] <= 9'b010001000; // zero $b
// memory[34] <= 9'b011001001; // addi $b, 1 memory[34] <= 9'b011001001; // addi $b, 1
// memory[35] <= 9'b101001010; // banks $b, $1 memory[35] <= 9'b101001010; // banks $b, $1
// memory[36] <= 9'b101111100; // jb Inc memory[36] <= 9'b101111100; // jb Inc
// // Check to see if any swaps have been made in the last iteration // Check to see if any swaps have been made in the last iteration
// // SwapChk: // SwapChk:
// memory[37] <= 9'b101001011; // bankl $b, $1 memory[37] <= 9'b101001011; // bankl $b, $1
// memory[38] <= 9'b110001001; // beq $b, JE memory[38] <= 9'b110001001; // beq $b, JE
// memory[39] <= 9'b100100001; // jf Reset memory[39] <= 9'b100100001; // jf Reset
// // JE: // JE:
// memory[40] <= 9'b100100011; // jf End memory[40] <= 9'b100100011; // jf End
// // Reset: // Reset:
// memory[41] <= 9'b010001000; // zero $b memory[41] <= 9'b010001000; // zero $b
// memory[42] <= 9'b101001000; // banks $b, $0 memory[42] <= 9'b101001000; // banks $b, $0
// memory[43] <= 9'b101111011; // jb LoadNext memory[43] <= 9'b101111011; // jb LoadNext
// // End: // End:
// memory[44] <= 9'b000000000; // halt memory[44] <= 9'b000000000; // halt
// Binary Search // Binary Search