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Comments and slight renames

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This commit is contained in:
WilliamMiceli
2019-02-15 17:49:12 -05:00
parent 32faa621d6
commit 6369170e41
1 changed files with 3 additions and 3 deletions
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6
lab2CA.srcs/sources_1/new/ALU.v
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@@ -1,7 +1,7 @@
`timescale 1ns / 1ps
module ALU(
input wire [2:0] opcode,
input wire [2:0] opcode, // NOT the same as the instruction set opcode
input wire [8:0] operand0,
input wire [8:0] operand1,
output wire [8:0] result
@@ -25,8 +25,8 @@ module ALU(
// H (111)
// MUX chooses which result to show based on the OPCODE
mux_8_1 mux_result(
// MUX chooses which result to show based on the ALU's opcode
mux_8_1 mux0(
.switch(opcode),
.A(result_A),
.B(result_B),