Framework of ALU is pretty much done

lab2CA.srcs/sim_1/new/ALU.v

@@ -0,0 +1,40 @@
+`timescale 1ns / 1ps
+
+module ALU(
+    input wire [8:0] instruction,
+    output wire [8:0] result 
+    );
+    
+    // Wires for connecting the modules to the mux
+    wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P;
+    
+    // Please place modules in order of OPCODE, to make them easier to find
+    
+    
+    
+    
+    
+    
+    
+    // MUX chooses which result to show based on the OPCODE
+    mux_16_1 mux_result(
+        .switch(instruction[8:5]),
+        .A(A),
+        .B(B),
+        .C(C),
+        .D(D),
+        .E(E),
+        .F(F),
+        .G(G),
+        .H(H),
+        .I(I),
+        .J(J),
+        .K(K),
+        .L(L),
+        .M(M),
+        .N(N),
+        .O(O),
+        .P(P),
+        .out(result));
+
+endmodule

lab2CA.xpr

@@ -3,7 +3,7 @@
 <!--                                                         -->
 <!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->
 
-<Project Version="7" Minor="39" Path="C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr">
+<Project Version="7" Minor="39" Path="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
     <Option Name="Id" Val="0a5803efda44405bb28bbf43ba22e808"/>
@@ -95,6 +95,14 @@
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
       <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sim_1/new/ALU.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="RegFile"/>