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case for control unit

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This commit is contained in:
jose.rodriguezlabra
2019-03-10 14:05:21 -04:00
parent 172238b4e0
commit 7406cddb64
1 changed files with 7 additions and 3 deletions
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10
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -1,8 +1,8 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module CPU9bits(input wire [8:0] instr, module CPU9bits(input wire [8:0] instr,
input wire reset, clk, input wire reset, clk,
output reg done output reg done
); );
wire [8:0] op1, op2; wire [8:0] op1, op2;
@@ -36,7 +36,11 @@ module CPU9bits(input wire [8:0] instr,
//Make control unit here //Make control unit here
always @(instr) begin
case (instr)
9'b000000000: //something
endcase
end
//------------------------------ //------------------------------