Making fixes to Bubble Sort
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16
lab2CA.xpr
16
lab2CA.xpr
@@ -3,7 +3,7 @@
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<!-- -->
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<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="39" Path="C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr">
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<Project Version="7" Minor="39" Path="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="0a5803efda44405bb28bbf43ba22e808"/>
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@@ -31,7 +31,7 @@
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="DSAVendor" Val="xilinx"/>
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<Option Name="DSANumComputeUnits" Val="60"/>
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<Option Name="WTXSimLaunchSim" Val="312"/>
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<Option Name="WTXSimLaunchSim" Val="338"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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@@ -156,6 +156,7 @@
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<Option Name="XSimWcfgFile" Val="$PPRDIR/regFile_tb_behav.wcfg"/>
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<Option Name="XSimWcfgFile" Val="$PPRDIR/CPU9bits_tb_behav1.wcfg"/>
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<Option Name="XSimWcfgFile" Val="$PPRDIR/Bank_behav1.wcfg"/>
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<Option Name="xsim.simulate.runtime" Val="100000ns"/>
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</Config>
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</FileSet>
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<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
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@@ -186,16 +187,20 @@
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<Runs Version="1" Minor="10">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k160tifbg484-2L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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@@ -206,7 +211,6 @@
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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</Run>
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