Activated all testbenches

README.md

@@ -10,7 +10,7 @@
 * Need to allow for signed numbers
 * Remove subtraction from ALU
 * Have arithmetic shift left and right
-* Uncomment all testbenches
+* <strike>Uncomment all testbenches</strike>
   * We can have multiple testbenches active at once
 * Bitwise operations do not need a 1-bit implementation, modify 9-bit and keep it only
 * Comparator needed

lab2CA.srcs/sources_1/new/ALU.v

@@ -62,47 +62,47 @@ module ALU(
 
 endmodule
 
-//testbench
+testbench
-//module alu_tb();
+module alu_tb();
-//reg [8:0] a;
+reg [8:0] a;
-//reg [8:0] b;
+reg [8:0] b;
-//reg [2:0] c;
+reg [2:0] c;
-//wire [8:0] d;
+wire [8:0] d;
 
-//ALU alu0(
+ALU alu0(
-//.operand0(a),
+.operand0(a),
-//.operand1(b),
+.operand1(b),
-//.opcode(c),
+.opcode(c),
-//.result(d));
+.result(d));
     
-//    initial begin
+   initial begin
-//    a = 9'b000000111;
+   a = 9'b000000111;
-//    b = 9'b000111000;
+   b = 9'b000111000;
-//    c = 3'b000;
+   c = 3'b000;
-//    #5
+   #5
-//    a = 9'b000011000;
+   a = 9'b000011000;
-//    b = 9'b000011000;
+   b = 9'b000011000;
-//    c = 3'b001;
+   c = 3'b001;
-//    #5
+   #5
-//    a = 9'b101010100;
+   a = 9'b101010100;
-//    b = 9'b010101011;
+   b = 9'b010101011;
-//    c = 3'b010;
+   c = 3'b010;
-//    #5
+   #5
-//    a = 9'b101010100;
+   a = 9'b101010100;
-//    b = 9'b010101000;
+   b = 9'b010101000;
-//    c = 3'b011;
+   c = 3'b011;
-//    #5
+   #5
-//    a = 9'b000110000;
+   a = 9'b000110000;
-//    b = 9'b000111000;
+   b = 9'b000111000;
-//    c = 3'b100;
+   c = 3'b100;
-//    #5
+   #5
-//    a = 9'b01011000;
+   a = 9'b01011000;
-//    c = 3'b101;
+   c = 3'b101;
-//    #5
+   #5
-//    a = 9'b00001010;
+   a = 9'b00001010;
-//    c = 3'b110;
+   c = 3'b110;
-//    #5
+   #5
-//    #5 $finish;
+   #5 $finish;
 
-//    end
+   end
-//endmodule
+endmodule

lab2CA.srcs/sources_1/new/FetchUnit.v

@@ -85,7 +85,8 @@ FetchUnit fetchUnit0(
     #5
     #5
     #5
-    #5 $finish;
+    #5
+    $finish;
 
     end
 endmodule