Shift right arithmetic implemented into ALU

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -847,6 +847,43 @@ module shift_right_logical_tb();
     end
 endmodule
 
+module shift_right_arithmetic(
+    input wire [8:0] A,
+    output wire [8:0] B);
+    
+    assign B = {A[8],A[8:1]};
+
+endmodule
+
+//testbench
+module shift_right_arithmetic_tb();
+    reg [8:0] a;
+    wire [8:0] b;
+
+    shift_right_arithmetic tb0(
+        .A(a),
+        .B(b));
+
+    initial begin
+        a = 9'b000000000;
+        #5
+        a = 9'b000000001;
+        #5
+        a = 9'b000111000;
+        #5
+        a = 9'b010101010;
+        #5
+        a = 9'b101010101;
+        #5
+        a = 9'b111111111;
+        #5
+        a = 9'b100000001;
+        #5
+        $finish;
+
+    end
+endmodule
+
 module sub_9bit(
     input wire [8:0] A,
     input wire [8:0] B,