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ALU now fully has 4-bit opcode

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WilliamMiceli
2019-03-12 11:12:21 -04:00
parent 1c5e79c1ec
commit 9ac8963fb0
1 changed files with 10 additions and 2 deletions
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12
lab2CA.srcs/sources_1/new/ALU.v
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@@ -8,7 +8,7 @@ module ALU(
); );
// Wires for connecting the modules to the mux // Wires for connecting the modules to the mux
wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H; wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H,result_I,result_J,result_K,result_L,result_M,result_N,result_O,result_P;
// A (0000) - Add // A (0000) - Add
add_9bit add0( add_9bit add0(
@@ -48,7 +48,7 @@ module ALU(
// MUX chooses which result to show based on the ALU's opcode // MUX chooses which result to show based on the ALU's opcode
mux_8_1 mux0( mux_16_1 mux0(
.switch(opcode), .switch(opcode),
.A(result_A), .A(result_A),
.B(result_B), .B(result_B),
@@ -58,6 +58,14 @@ module ALU(
.F(result_F), .F(result_F),
.G(result_G), .G(result_G),
.H(result_H), .H(result_H),
.I(result_I),
.J(result_J),
.K(result_K),
.L(result_L),
.M(result_M),
.N(result_N),
.O(result_O),
.P(result_P),
.out(result)); .out(result));
endmodule endmodule