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This commit is contained in:
goochey
2019-02-20 11:40:43 -05:00
parent 6550b48599
commit 9ba63880bd
33 changed files with 234 additions and 197 deletions
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54
lab2CA.cache/wt/webtalk_pa.xml
View File

@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Sat Feb 16 17:40:52 2019"> <application name="pa" timeStamp="Wed Feb 20 11:35:47 2019">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="88e779ed22f94d2db93b335d17c75f15" type="ProjectID"/> <property name="ProjectID" value="88e779ed22f94d2db93b335d17c75f15" type="ProjectID"/>
<property name="ProjectIteration" value="5" type="ProjectIteration"/> <property name="ProjectIteration" value="7" type="ProjectIteration"/>
</section> </section>
<section name="PlanAhead Usage" visible="true"> <section name="PlanAhead Usage" visible="true">
<item name="Project Data"> <item name="Project Data">
@@ -18,31 +18,34 @@ This means code written to parse this file will need to be revisited each subseq
</item> </item>
<item name="Java Command Handlers"> <item name="Java Command Handlers">
<property name="OpenDesign" value="1" type="JavaHandler"/> <property name="OpenDesign" value="1" type="JavaHandler"/>
<property name="OpenProject" value="1" type="JavaHandler"/>
<property name="ReloadDesign" value="1" type="JavaHandler"/> <property name="ReloadDesign" value="1" type="JavaHandler"/>
<property name="RunImplementation" value="5" type="JavaHandler"/> <property name="RunImplementation" value="7" type="JavaHandler"/>
<property name="RunSchematic" value="9" type="JavaHandler"/> <property name="RunSchematic" value="9" type="JavaHandler"/>
<property name="RunSynthesis" value="16" type="JavaHandler"/> <property name="RunSynthesis" value="16" type="JavaHandler"/>
<property name="SetSourceEnabled" value="2" type="JavaHandler"/> <property name="SetSourceEnabled" value="2" type="JavaHandler"/>
<property name="SetTopNode" value="21" type="JavaHandler"/> <property name="SetTopNode" value="22" type="JavaHandler"/>
<property name="ShowView" value="9" type="JavaHandler"/> <property name="ShowView" value="9" type="JavaHandler"/>
<property name="SimulationClose" value="4" type="JavaHandler"/> <property name="SimulationClose" value="4" type="JavaHandler"/>
<property name="SimulationRun" value="48" type="JavaHandler"/> <property name="SimulationRun" value="62" type="JavaHandler"/>
<property name="ToggleSelectAreaMode" value="2" type="JavaHandler"/> <property name="ToggleSelectAreaMode" value="2" type="JavaHandler"/>
<property name="ToolsSettings" value="1" type="JavaHandler"/> <property name="ToolsSettings" value="1" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="1" type="JavaHandler"/> <property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
<property name="ViewTaskProjectManager" value="1" type="JavaHandler"/>
<property name="ViewTaskRTLAnalysis" value="1" type="JavaHandler"/> <property name="ViewTaskRTLAnalysis" value="1" type="JavaHandler"/>
<property name="ZoomFit" value="6" type="JavaHandler"/> <property name="ZoomFit" value="6" type="JavaHandler"/>
</item> </item>
<item name="Gui Handlers"> <item name="Gui Handlers">
<property name="BaseDialog_CANCEL" value="12" type="GuiHandlerData"/> <property name="BaseDialog_CANCEL" value="12" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="59" type="GuiHandlerData"/> <property name="BaseDialog_OK" value="65" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="3" type="GuiHandlerData"/> <property name="BaseDialog_YES" value="4" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="4" type="GuiHandlerData"/> <property name="CmdMsgDialog_OK" value="4" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/> <property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="109" type="GuiHandlerData"/> <property name="FileSetPanel_FILE_SET_PANEL_TREE" value="122" type="GuiHandlerData"/>
<property name="FloatingTopDialog_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="8" type="GuiHandlerData"/> <property name="FloatingTopDialog_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="12" type="GuiHandlerData"/>
<property name="FloatingTopDialog_SPECIFY_NEW_TOP_MODULE" value="8" type="GuiHandlerData"/> <property name="FloatingTopDialog_SPECIFY_NEW_TOP_MODULE" value="10" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="100" type="GuiHandlerData"/> <property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="119" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="26" type="GuiHandlerData"/> <property name="GraphicalView_ZOOM_FIT" value="26" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="40" type="GuiHandlerData"/> <property name="GraphicalView_ZOOM_IN" value="40" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="28" type="GuiHandlerData"/> <property name="GraphicalView_ZOOM_OUT" value="28" type="GuiHandlerData"/>
@@ -52,46 +55,43 @@ This means code written to parse this file will need to be revisited each subseq
<property name="HCodeEditor_DIFF_WITH" value="3" type="GuiHandlerData"/> <property name="HCodeEditor_DIFF_WITH" value="3" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="5" type="GuiHandlerData"/> <property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="5" type="GuiHandlerData"/>
<property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="13" type="GuiHandlerData"/> <property name="HInputHandler_TOGGLE_LINE_COMMENTS" value="13" type="GuiHandlerData"/>
<property name="LaunchPanel_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="2" type="GuiHandlerData"/> <property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="2" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="22" type="GuiHandlerData"/> <property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="22" type="GuiHandlerData"/>
<property name="OpenFileAction_OK" value="1" type="GuiHandlerData"/> <property name="OpenFileAction_OK" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_AUTO_UPDATE_HIER" value="24" type="GuiHandlerData"/> <property name="PACommandNames_AUTO_UPDATE_HIER" value="25" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_RTL_DESIGN" value="1" type="GuiHandlerData"/> <property name="PACommandNames_OPEN_RTL_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RELOAD_RTL_DESIGN" value="1" type="GuiHandlerData"/> <property name="PACommandNames_RELOAD_RTL_DESIGN" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SELECT_AREA" value="2" type="GuiHandlerData"/> <property name="PACommandNames_SELECT_AREA" value="2" type="GuiHandlerData"/>
<property name="PACommandNames_SET_AS_TOP" value="22" type="GuiHandlerData"/> <property name="PACommandNames_SET_AS_TOP" value="23" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="45" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="60" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_FUNCTIONAL" value="1" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_FUNCTIONAL" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_TIMING" value="4" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_RUN_POST_IMPLEMENTATION_TIMING" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_SETTINGS" value="1" type="GuiHandlerData"/> <property name="PACommandNames_SIMULATION_SETTINGS" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_ENABLE" value="1" type="GuiHandlerData"/> <property name="PACommandNames_SRC_ENABLE" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ZOOM_FIT" value="6" type="GuiHandlerData"/> <property name="PACommandNames_ZOOM_FIT" value="6" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="6" type="GuiHandlerData"/> <property name="PAViews_CODE" value="6" type="GuiHandlerData"/>
<property name="PAViews_PROJECT_SUMMARY" value="28" type="GuiHandlerData"/> <property name="PAViews_PROJECT_SUMMARY" value="40" type="GuiHandlerData"/>
<property name="PAViews_SCHEMATIC" value="9" type="GuiHandlerData"/> <property name="PAViews_SCHEMATIC" value="9" type="GuiHandlerData"/>
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/> <property name="ProgressDialog_BACKGROUND" value="3" type="GuiHandlerData"/>
<property name="ProgressDialog_CANCEL" value="4" type="GuiHandlerData"/> <property name="ProgressDialog_CANCEL" value="4" type="GuiHandlerData"/>
<property name="ProjectTab_RELOAD" value="8" type="GuiHandlerData"/> <property name="ProjectTab_RELOAD" value="8" type="GuiHandlerData"/>
<property name="RDICommands_COPY" value="2" type="GuiHandlerData"/> <property name="RDICommands_COPY" value="2" type="GuiHandlerData"/>
<property name="RDICommands_REDO" value="1" type="GuiHandlerData"/> <property name="RDICommands_REDO" value="1" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="32" type="GuiHandlerData"/> <property name="RDICommands_SAVE_FILE" value="48" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="295" type="GuiHandlerData"/> <property name="RDIViews_WAVEFORM_VIEWER" value="338" type="GuiHandlerData"/>
<property name="RunGadget_SHOW_ERROR" value="1" type="GuiHandlerData"/> <property name="RunGadget_SHOW_ERROR" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/> <property name="SaveProjectUtils_CANCEL" value="1" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="5" type="GuiHandlerData"/> <property name="SaveProjectUtils_SAVE" value="5" type="GuiHandlerData"/>
<property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="8" type="GuiHandlerData"/> <property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="12" type="GuiHandlerData"/>
<property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="3" type="GuiHandlerData"/> <property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="3" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="25" type="GuiHandlerData"/> <property name="SrcMenu_IP_HIERARCHY" value="26" type="GuiHandlerData"/>
<property name="StaleMoreAction_OUT_OF_DATE_DETAILS" value="1" type="GuiHandlerData"/> <property name="StaleMoreAction_OUT_OF_DATE_DETAILS" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="1" type="GuiHandlerData"/> <property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="1" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="15" type="GuiHandlerData"/> <property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
<property name="TaskBanner_CLOSE" value="17" type="GuiHandlerData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/> <property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="88" type="GuiHandlerData"/> <property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="148" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="5" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="4" type="TclMode"/>
</item> </item>
</section> </section>
</application> </application>

11
lab2CA.runs/.jobs/vrs_config_21.xml Normal file
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@@ -0,0 +1,11 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

11
lab2CA.runs/.jobs/vrs_config_22.xml Normal file
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@@ -0,0 +1,11 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>

3
lab2CA.runs/impl_1/FetchUnit.tcl
View File

@@ -60,9 +60,6 @@ proc step_failed { step } {
close $ch close $ch
} }
set_msg_config -id {Common 17-41} -limit 10000000
set_msg_config -id {Synth 8-256} -limit 10000
set_msg_config -id {Synth 8-638} -limit 10000
start_step init_design start_step init_design
set ACTIVE_STEP init_design set ACTIVE_STEP init_design

196
lab2CA.runs/impl_1/FetchUnit.vdi
View File

@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit) # Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Feb 16 17:35:59 2019 # Start of session at: Wed Feb 20 11:36:21 2019
# Process ID: 3548 # Process ID: 644
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log FetchUnit.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source FetchUnit.tcl -notrace # Command line: vivado.exe -log FetchUnit.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source FetchUnit.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit.vdi # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit.vdi
@@ -16,13 +16,13 @@ Design is defaulting to constrset: constrs_1
INFO: [Project 1-479] Netlist was created with Vivado 2018.3 INFO: [Project 1-479] Netlist was created with Vivado 2018.3
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 578.453 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 577.652 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary: INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed. No Unisim elements were transformed.
4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. 4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully link_design completed successfully
link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:16 . Memory (MB): peak = 584.031 ; gain = 333.246 link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:16 . Memory (MB): peak = 583.164 ; gain = 318.402
Command: opt_design Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
@@ -33,53 +33,53 @@ INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.760 . Memory (MB): peak = 598.289 ; gain = 14.258 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.704 . Memory (MB): peak = 597.828 ; gain = 14.664
Starting Cache Timing Information Task Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 3da38fa8 Ending Cache Timing Information Task | Checksum: 6a15e7bd
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1160.113 ; gain = 561.824 Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1157.887 ; gain = 560.059
Starting Logic Optimization Task Starting Logic Optimization Task
Phase 1 Retarget Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s). INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 3da38fa8 Phase 1 Retarget | Checksum: 6a15e7bd
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1256.469 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1254.445 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 3da38fa8 Phase 2 Constant propagation | Checksum: 6a15e7bd
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1256.469 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1254.445 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep Phase 3 Sweep
Phase 3 Sweep | Checksum: 3da38fa8 Phase 3 Sweep | Checksum: 6a15e7bd
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1256.469 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1254.445 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 3da38fa8 Phase 4 BUFG optimization | Checksum: 6a15e7bd
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1256.469 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1254.445 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 3da38fa8 Phase 5 Shift Register Optimization | Checksum: 6a15e7bd
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.095 . Memory (MB): peak = 1256.469 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 1254.445 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 3da38fa8 Phase 6 Post Processing Netlist | Checksum: 6a15e7bd
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.096 . Memory (MB): peak = 1256.469 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.073 . Memory (MB): peak = 1254.445 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary Opt_design Change Summary
========================= =========================
@@ -100,32 +100,32 @@ Opt_design Change Summary
Starting Connectivity Check Task Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1256.469 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1254.445 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 3da38fa8 Ending Logic Optimization Task | Checksum: 6a15e7bd
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.098 . Memory (MB): peak = 1256.469 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1254.445 ; gain = 0.000
Starting Power Optimization Task Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 3da38fa8 Ending Power Optimization Task | Checksum: 6a15e7bd
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1256.469 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1254.445 ; gain = 0.000
Starting Final Cleanup Task Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 3da38fa8 Ending Final Cleanup Task | Checksum: 6a15e7bd
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1254.445 ; gain = 0.000
Starting Netlist Obfuscation Task Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1254.445 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 3da38fa8 Ending Netlist Obfuscation Task | Checksum: 6a15e7bd
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1254.445 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation INFO: [Common 17-83] Releasing license: Implementation
20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. 20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully opt_design completed successfully
opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1256.469 ; gain = 672.438 opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1254.445 ; gain = 671.281
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1254.445 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write. WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_opt.dcp' has been generated. INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_opt.dcp' has been generated.
@@ -154,127 +154,127 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of
Phase 1 Placer Initialization Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1254.445 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2dee624c Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2dee624c
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1256.469 ; gain = 0.000 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1254.445 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1256.469 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1254.445 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: c3ac8419 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f86a639b
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.988 ; gain = 6.543
Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 17eb8b195 Phase 1.3 Build Placer Netlist Model | Checksum: 1b3769117
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.988 ; gain = 6.543
Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 17eb8b195 Phase 1.4 Constrain Clocks/Macros | Checksum: 1b3769117
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.988 ; gain = 6.543
Phase 1 Placer Initialization | Checksum: 17eb8b195 Phase 1 Placer Initialization | Checksum: 1b3769117
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.031 ; gain = 3.563 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1260.988 ; gain = 6.543
Phase 2 Global Placement Phase 2 Global Placement
Phase 2.1 Floorplanning Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 17eb8b195 Phase 2.1 Floorplanning | Checksum: 1b3769117
Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1261.789 ; gain = 5.320 Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1262.563 ; gain = 8.117
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
Phase 2 Global Placement | Checksum: c93401db Phase 2 Global Placement | Checksum: fdf1e15d
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1271.574 ; gain = 17.129
Phase 3 Detail Placement Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: c93401db Phase 3.1 Commit Multi Column Macros | Checksum: fdf1e15d
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1271.574 ; gain = 17.129
Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 13d5628d5 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 172140857
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1271.574 ; gain = 17.129
Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1566ae30c Phase 3.3 Area Swap Optimization | Checksum: 18b28c28e
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1271.574 ; gain = 17.129
Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1566ae30c Phase 3.4 Pipeline Register Optimization | Checksum: 18b28c28e
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1270.621 ; gain = 14.152 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1271.574 ; gain = 17.129
Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 179d3e6f9 Phase 3.5 Small Shape Detail Placement | Checksum: 1814d396b
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 179d3e6f9 Phase 3.6 Re-assign LUT pins | Checksum: 1814d396b
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 179d3e6f9 Phase 3.7 Pipeline Register Optimization | Checksum: 1814d396b
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
Phase 3 Detail Placement | Checksum: 179d3e6f9 Phase 3 Detail Placement | Checksum: 1814d396b
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
Phase 4 Post Placement Optimization and Clean-Up Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 179d3e6f9 Phase 4.1 Post Commit Optimization | Checksum: 1814d396b
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 179d3e6f9 Phase 4.2 Post Placement Cleanup | Checksum: 1814d396b
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 179d3e6f9 Phase 4.3 Placer Reporting | Checksum: 1814d396b
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1280.449 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1281.449 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 1f8cde3fa Phase 4.4 Final Placement Cleanup | Checksum: 20047366c
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1f8cde3fa Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20047366c
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
Ending Placer Task | Checksum: 12070b279 Ending Placer Task | Checksum: 127ea04eb
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1280.449 ; gain = 23.980 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1281.449 ; gain = 27.004
INFO: [Common 17-83] Releasing license: Implementation INFO: [Common 17-83] Releasing license: Implementation
37 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. 37 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully place_design completed successfully
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1280.449 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1281.449 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write. WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database... Writing placer database...
Writing XDEF routing. Writing XDEF routing.
Writing XDEF routing logical nets. Writing XDEF routing logical nets.
Writing XDEF routing special nets. Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.094 . Memory (MB): peak = 1280.449 ; gain = 0.000 Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 1281.449 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_placed.dcp' has been generated. INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file FetchUnit_io_placed.rpt INFO: [runtcl-4] Executing : report_io -file FetchUnit_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1280.449 ; gain = 0.000 report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.058 . Memory (MB): peak = 1281.449 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file FetchUnit_utilization_placed.rpt -pb FetchUnit_utilization_placed.pb INFO: [runtcl-4] Executing : report_utilization -file FetchUnit_utilization_placed.rpt -pb FetchUnit_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file FetchUnit_control_sets_placed.rpt INFO: [runtcl-4] Executing : report_control_sets -verbose -file FetchUnit_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1280.449 ; gain = 0.000 report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1281.449 ; gain = 0.000
Command: route_design Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti'
@@ -286,12 +286,12 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in
Starting Routing Task Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 80d46943 ConstDB: 0 ShapeSum: 9f9c4936 RouteDB: 0 Checksum: PlaceDB: 884dbbb5 ConstDB: 0 ShapeSum: 9f9c4936 RouteDB: 0
Phase 1 Build RT Design Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: c942aae2 Phase 1 Build RT Design | Checksum: c942aae2
Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1491.852 ; gain = 211.402 Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 1488.156 ; gain = 206.707
Post Restoration Checksum: NetGraph: 96738515 NumContArr: 32cf25cd Constraints: 0 Timing: 0 Post Restoration Checksum: NetGraph: 96738515 NumContArr: 32cf25cd Constraints: 0 Timing: 0
Phase 2 Router Initialization Phase 2 Router Initialization
@@ -300,21 +300,21 @@ INFO: [Route 35-64] No timing constraints were detected. The router will operate
Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: c942aae2 Phase 2.1 Fix Topology Constraints | Checksum: c942aae2
Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1496.797 ; gain = 216.348 Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 1492.688 ; gain = 211.238
Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: c942aae2 Phase 2.2 Pre Route Cleanup | Checksum: c942aae2
Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1496.797 ; gain = 216.348 Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 1492.688 ; gain = 211.238
Number of Nodes with overlaps = 0 Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: a27c41a8 Phase 2 Router Initialization | Checksum: a27c41a8
Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 1520.801 ; gain = 240.352 Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.094 ; gain = 234.645
Phase 3 Initial Routing Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 15301da77 Phase 3 Initial Routing | Checksum: 15301da77
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.094 ; gain = 234.645
Phase 4 Rip-up And Reroute Phase 4 Rip-up And Reroute
@@ -323,25 +323,25 @@ Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 0 Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: af31d432 Phase 4.1 Global Iteration 0 | Checksum: af31d432
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
Phase 4 Rip-up And Reroute | Checksum: af31d432 Phase 4 Rip-up And Reroute | Checksum: af31d432
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: af31d432 Phase 5 Delay and Skew Optimization | Checksum: af31d432
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
Phase 6 Post Hold Fix Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: af31d432 Phase 6.1 Hold Fix Iter | Checksum: af31d432
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
Phase 6 Post Hold Fix | Checksum: af31d432 Phase 6 Post Hold Fix | Checksum: af31d432
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
Phase 7 Route finalize Phase 7 Route finalize
@@ -384,36 +384,36 @@ Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: af31d432 Phase 7 Route finalize | Checksum: af31d432
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
Phase 8 Verifying routed nets Phase 8 Verifying routed nets
Verification completed successfully Verification completed successfully
Phase 8 Verifying routed nets | Checksum: af31d432 Phase 8 Verifying routed nets | Checksum: af31d432
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
Phase 9 Depositing Routes Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 4b1641fa Phase 9 Depositing Routes | Checksum: 4b1641fa
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
INFO: [Route 35-16] Router Completed Successfully INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 1520.801 ; gain = 240.352 Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1516.094 ; gain = 234.645
Routing Is Done. Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation INFO: [Common 17-83] Releasing license: Implementation
49 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. 49 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully route_design completed successfully
route_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 1520.801 ; gain = 240.352 route_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 1516.094 ; gain = 234.645
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1520.801 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1516.094 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write. WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
Writing placer database... Writing placer database...
Writing XDEF routing. Writing XDEF routing.
Writing XDEF routing logical nets. Writing XDEF routing logical nets.
Writing XDEF routing special nets. Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1520.801 ; gain = 0.000 Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1516.094 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_routed.dcp' has been generated. INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx INFO: [runtcl-4] Executing : report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx
Command: report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx Command: report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx
@@ -448,4 +448,4 @@ INFO: [runtcl-4] Executing : report_clock_utilization -file FetchUnit_clock_util
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file FetchUnit_bus_skew_routed.rpt -pb FetchUnit_bus_skew_routed.pb -rpx FetchUnit_bus_skew_routed.rpx INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file FetchUnit_bus_skew_routed.rpt -pb FetchUnit_bus_skew_routed.pb -rpx FetchUnit_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Sat Feb 16 17:37:11 2019... INFO: [Common 17-206] Exiting Vivado at Wed Feb 20 11:37:30 2019...

2
lab2CA.runs/impl_1/FetchUnit_bus_skew_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Feb 16 17:37:11 2019 | Date : Wed Feb 20 11:37:30 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file FetchUnit_bus_skew_routed.rpt -pb FetchUnit_bus_skew_routed.pb -rpx FetchUnit_bus_skew_routed.rpx | Command : report_bus_skew -warn_on_violation -file FetchUnit_bus_skew_routed.rpt -pb FetchUnit_bus_skew_routed.pb -rpx FetchUnit_bus_skew_routed.rpx
| Design : FetchUnit | Design : FetchUnit

2
lab2CA.runs/impl_1/FetchUnit_clock_utilization_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Feb 16 17:37:11 2019 | Date : Wed Feb 20 11:37:30 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_clock_utilization -file FetchUnit_clock_utilization_routed.rpt | Command : report_clock_utilization -file FetchUnit_clock_utilization_routed.rpt
| Design : FetchUnit | Design : FetchUnit

2
lab2CA.runs/impl_1/FetchUnit_control_sets_placed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Feb 16 17:36:37 2019 | Date : Wed Feb 20 11:36:57 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file FetchUnit_control_sets_placed.rpt | Command : report_control_sets -verbose -file FetchUnit_control_sets_placed.rpt
| Design : FetchUnit | Design : FetchUnit

6
lab2CA.runs/impl_1/FetchUnit_drc_opted.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Feb 16 17:36:34 2019 | Date : Wed Feb 20 11:36:55 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_drc -file FetchUnit_drc_opted.rpt -pb FetchUnit_drc_opted.pb -rpx FetchUnit_drc_opted.rpx | Command : report_drc -file FetchUnit_drc_opted.rpt -pb FetchUnit_drc_opted.pb -rpx FetchUnit_drc_opted.rpx
| Design : FetchUnit | Design : FetchUnit
@@ -37,12 +37,12 @@ Table of Contents
----------------- -----------------
NSTD-1#1 Critical Warning NSTD-1#1 Critical Warning
Unspecified I/O Standard Unspecified I/O Standard
21 out of 21 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], clk, op_idx, reset. 21 out of 21 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], op_idx[0], clk, reset.
Related violations: <none> Related violations: <none>
UCIO-1#1 Critical Warning UCIO-1#1 Critical Warning
Unconstrained Logical Port Unconstrained Logical Port
21 out of 21 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], clk, op_idx, reset. 21 out of 21 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], op_idx[0], clk, reset.
Related violations: <none> Related violations: <none>
CFGBVS-1#1 Warning CFGBVS-1#1 Warning

6
lab2CA.runs/impl_1/FetchUnit_drc_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Feb 16 17:37:10 2019 | Date : Wed Feb 20 11:37:29 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx | Command : report_drc -file FetchUnit_drc_routed.rpt -pb FetchUnit_drc_routed.pb -rpx FetchUnit_drc_routed.rpx
| Design : FetchUnit | Design : FetchUnit
@@ -37,12 +37,12 @@ Table of Contents
----------------- -----------------
NSTD-1#1 Critical Warning NSTD-1#1 Critical Warning
Unspecified I/O Standard Unspecified I/O Standard
21 out of 21 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], clk, op_idx, reset. 21 out of 21 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], op_idx[0], clk, reset.
Related violations: <none> Related violations: <none>
UCIO-1#1 Critical Warning UCIO-1#1 Critical Warning
Unconstrained Logical Port Unconstrained Logical Port
21 out of 21 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], clk, op_idx, reset. 21 out of 21 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: AddrIn[8:0], AddrOut[8:0], op_idx[0], clk, reset.
Related violations: <none> Related violations: <none>
CFGBVS-1#1 Warning CFGBVS-1#1 Warning

6
lab2CA.runs/impl_1/FetchUnit_io_placed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Feb 16 17:36:37 2019 | Date : Wed Feb 20 11:36:57 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_io -file FetchUnit_io_placed.rpt | Command : report_io -file FetchUnit_io_placed.rpt
| Design : FetchUnit | Design : FetchUnit
@@ -25,7 +25,7 @@ Table of Contents
+---------------+ +---------------+
| Total User IO | | Total User IO |
+---------------+ +---------------+
| 21 | | 22 |
+---------------+ +---------------+
@@ -424,7 +424,7 @@ Table of Contents
| T13 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | | T13 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
| T14 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | | | T14 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | |
| T15 | AddrIn[2] | High Range | IO_L24P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | | T15 | AddrIn[2] | High Range | IO_L24P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| T16 | op_idx | High Range | IO_L20N_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | | T16 | op_idx[0] | High Range | IO_L20N_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | |
| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| T18 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | | T18 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
| T19 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | | | T19 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | |

2
lab2CA.runs/impl_1/FetchUnit_methodology_drc_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Feb 16 17:37:11 2019 | Date : Wed Feb 20 11:37:30 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_methodology -file FetchUnit_methodology_drc_routed.rpt -pb FetchUnit_methodology_drc_routed.pb -rpx FetchUnit_methodology_drc_routed.rpx | Command : report_methodology -file FetchUnit_methodology_drc_routed.rpt -pb FetchUnit_methodology_drc_routed.pb -rpx FetchUnit_methodology_drc_routed.rpx
| Design : FetchUnit | Design : FetchUnit

BIN
lab2CA.runs/impl_1/FetchUnit_opt.dcp
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Binary file not shown.

BIN
lab2CA.runs/impl_1/FetchUnit_placed.dcp
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Binary file not shown.

2
lab2CA.runs/impl_1/FetchUnit_power_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Feb 16 17:37:11 2019 | Date : Wed Feb 20 11:37:30 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_power -file FetchUnit_power_routed.rpt -pb FetchUnit_power_summary_routed.pb -rpx FetchUnit_power_routed.rpx | Command : report_power -file FetchUnit_power_routed.rpt -pb FetchUnit_power_summary_routed.pb -rpx FetchUnit_power_routed.rpx
| Design : FetchUnit | Design : FetchUnit

BIN
lab2CA.runs/impl_1/FetchUnit_routed.dcp
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Binary file not shown.

2
lab2CA.runs/impl_1/FetchUnit_timing_summary_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Feb 16 17:37:11 2019 | Date : Wed Feb 20 11:37:30 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_timing_summary -max_paths 10 -file FetchUnit_timing_summary_routed.rpt -pb FetchUnit_timing_summary_routed.pb -rpx FetchUnit_timing_summary_routed.rpx -warn_on_violation | Command : report_timing_summary -max_paths 10 -file FetchUnit_timing_summary_routed.rpt -pb FetchUnit_timing_summary_routed.pb -rpx FetchUnit_timing_summary_routed.rpx -warn_on_violation
| Design : FetchUnit | Design : FetchUnit

2
lab2CA.runs/impl_1/FetchUnit_utilization_placed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Feb 16 17:36:37 2019 | Date : Wed Feb 20 11:36:57 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_utilization -file FetchUnit_utilization_placed.rpt -pb FetchUnit_utilization_placed.pb | Command : report_utilization -file FetchUnit_utilization_placed.rpt -pb FetchUnit_utilization_placed.pb
| Design : FetchUnit | Design : FetchUnit

36
lab2CA.runs/impl_1/gen_run.xml
View File

@@ -1,50 +1,69 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550356552"> <GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550680547">
<File Type="BITSTR-BMM" Name="FetchUnit_bd.bmm"/>
<File Type="OPT-METHODOLOGY-DRC" Name="FetchUnit_methodology_drc_opted.rpt"/>
<File Type="INIT-TIMING" Name="FetchUnit_timing_summary_init.rpt"/>
<File Type="ROUTE-PWR" Name="FetchUnit_power_routed.rpt"/> <File Type="ROUTE-PWR" Name="FetchUnit_power_routed.rpt"/>
<File Type="PA-TCL" Name="FetchUnit.tcl"/> <File Type="PA-TCL" Name="FetchUnit.tcl"/>
<File Type="BITSTR-BMM" Name="FetchUnit_bd.bmm"/> <File Type="OPT-TIMING" Name="FetchUnit_timing_summary_opted.rpt"/>
<File Type="OPT-DCP" Name="FetchUnit_opt.dcp"/>
<File Type="ROUTE-PWR-SUM" Name="FetchUnit_power_summary_routed.pb"/> <File Type="ROUTE-PWR-SUM" Name="FetchUnit_power_summary_routed.pb"/>
<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/> <File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
<File Type="OPT-DCP" Name="FetchUnit_opt.dcp"/>
<File Type="OPT-DRC" Name="FetchUnit_drc_opted.rpt"/> <File Type="OPT-DRC" Name="FetchUnit_drc_opted.rpt"/>
<File Type="OPT-HWDEF" Name="FetchUnit.hwdef"/> <File Type="OPT-HWDEF" Name="FetchUnit.hwdef"/>
<File Type="PWROPT-DCP" Name="FetchUnit_pwropt.dcp"/> <File Type="PWROPT-DCP" Name="FetchUnit_pwropt.dcp"/>
<File Type="PWROPT-DRC" Name="FetchUnit_drc_pwropted.rpt"/>
<File Type="PWROPT-TIMING" Name="FetchUnit_timing_summary_pwropted.rpt"/>
<File Type="PLACE-DCP" Name="FetchUnit_placed.dcp"/> <File Type="PLACE-DCP" Name="FetchUnit_placed.dcp"/>
<File Type="PLACE-IO" Name="FetchUnit_io_placed.rpt"/> <File Type="PLACE-IO" Name="FetchUnit_io_placed.rpt"/>
<File Type="PLACE-CLK" Name="FetchUnit_clock_utilization_placed.rpt"/>
<File Type="PLACE-UTIL" Name="FetchUnit_utilization_placed.rpt"/> <File Type="PLACE-UTIL" Name="FetchUnit_utilization_placed.rpt"/>
<File Type="PLACE-UTIL-PB" Name="FetchUnit_utilization_placed.pb"/> <File Type="PLACE-UTIL-PB" Name="FetchUnit_utilization_placed.pb"/>
<File Type="PLACE-CTRL" Name="FetchUnit_control_sets_placed.rpt"/> <File Type="PLACE-CTRL" Name="FetchUnit_control_sets_placed.rpt"/>
<File Type="PLACE-SIMILARITY" Name="FetchUnit_incremental_reuse_placed.rpt"/>
<File Type="PLACE-PRE-SIMILARITY" Name="FetchUnit_incremental_reuse_pre_placed.rpt"/> <File Type="PLACE-PRE-SIMILARITY" Name="FetchUnit_incremental_reuse_pre_placed.rpt"/>
<File Type="BG-BGN" Name="FetchUnit.bgn"/> <File Type="BG-BGN" Name="FetchUnit.bgn"/>
<File Type="PLACE-TIMING" Name="FetchUnit_timing_summary_placed.rpt"/>
<File Type="POSTPLACE-PWROPT-DCP" Name="FetchUnit_postplace_pwropt.dcp"/> <File Type="POSTPLACE-PWROPT-DCP" Name="FetchUnit_postplace_pwropt.dcp"/>
<File Type="BG-BIN" Name="FetchUnit.bin"/> <File Type="BG-BIN" Name="FetchUnit.bin"/>
<File Type="POSTPLACE-PWROPT-TIMING" Name="FetchUnit_timing_summary_postplace_pwropted.rpt"/>
<File Type="PHYSOPT-DCP" Name="FetchUnit_physopt.dcp"/> <File Type="PHYSOPT-DCP" Name="FetchUnit_physopt.dcp"/>
<File Type="PHYSOPT-DRC" Name="FetchUnit_drc_physopted.rpt"/>
<File Type="BITSTR-MSK" Name="FetchUnit.msk"/> <File Type="BITSTR-MSK" Name="FetchUnit.msk"/>
<File Type="PHYSOPT-TIMING" Name="FetchUnit_timing_summary_physopted.rpt"/>
<File Type="ROUTE-ERROR-DCP" Name="FetchUnit_routed_error.dcp"/> <File Type="ROUTE-ERROR-DCP" Name="FetchUnit_routed_error.dcp"/>
<File Type="ROUTE-DCP" Name="FetchUnit_routed.dcp"/> <File Type="ROUTE-DCP" Name="FetchUnit_routed.dcp"/>
<File Type="ROUTE-BLACKBOX-DCP" Name="FetchUnit_routed_bb.dcp"/> <File Type="ROUTE-BLACKBOX-DCP" Name="FetchUnit_routed_bb.dcp"/>
<File Type="ROUTE-DRC" Name="FetchUnit_drc_routed.rpt"/> <File Type="ROUTE-DRC" Name="FetchUnit_drc_routed.rpt"/>
<File Type="ROUTE-DRC-PB" Name="FetchUnit_drc_routed.pb"/> <File Type="ROUTE-DRC-PB" Name="FetchUnit_drc_routed.pb"/>
<File Type="ROUTE-DRC-RPX" Name="FetchUnit_drc_routed.rpx"/> <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
<File Type="BITSTR-LTX" Name="FetchUnit.ltx"/> <File Type="BITSTR-LTX" Name="FetchUnit.ltx"/>
<File Type="ROUTE-METHODOLOGY-DRC" Name="FetchUnit_methodology_drc_routed.rpt"/> <File Type="ROUTE-DRC-RPX" Name="FetchUnit_drc_routed.rpx"/>
<File Type="BITSTR-MMI" Name="FetchUnit.mmi"/> <File Type="BITSTR-MMI" Name="FetchUnit.mmi"/>
<File Type="ROUTE-METHODOLOGY-DRC" Name="FetchUnit_methodology_drc_routed.rpt"/>
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="FetchUnit_methodology_drc_routed.rpx"/> <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="FetchUnit_methodology_drc_routed.rpx"/>
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="FetchUnit_methodology_drc_routed.pb"/>
<File Type="BITSTR-SYSDEF" Name="FetchUnit.sysdef"/> <File Type="BITSTR-SYSDEF" Name="FetchUnit.sysdef"/>
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="FetchUnit_methodology_drc_routed.pb"/>
<File Type="ROUTE-PWR-RPX" Name="FetchUnit_power_routed.rpx"/> <File Type="ROUTE-PWR-RPX" Name="FetchUnit_power_routed.rpx"/>
<File Type="ROUTE-STATUS" Name="FetchUnit_route_status.rpt"/> <File Type="ROUTE-STATUS" Name="FetchUnit_route_status.rpt"/>
<File Type="ROUTE-STATUS-PB" Name="FetchUnit_route_status.pb"/> <File Type="ROUTE-STATUS-PB" Name="FetchUnit_route_status.pb"/>
<File Type="ROUTE-TIMINGSUMMARY" Name="FetchUnit_timing_summary_routed.rpt"/> <File Type="ROUTE-TIMINGSUMMARY" Name="FetchUnit_timing_summary_routed.rpt"/>
<File Type="ROUTE-TIMING-PB" Name="FetchUnit_timing_summary_routed.pb"/> <File Type="ROUTE-TIMING-PB" Name="FetchUnit_timing_summary_routed.pb"/>
<File Type="ROUTE-TIMING-RPX" Name="FetchUnit_timing_summary_routed.rpx"/> <File Type="ROUTE-TIMING-RPX" Name="FetchUnit_timing_summary_routed.rpx"/>
<File Type="ROUTE-SIMILARITY" Name="FetchUnit_incremental_reuse_routed.rpt"/>
<File Type="ROUTE-CLK" Name="FetchUnit_clock_utilization_routed.rpt"/> <File Type="ROUTE-CLK" Name="FetchUnit_clock_utilization_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW" Name="FetchUnit_bus_skew_routed.rpt"/> <File Type="ROUTE-BUS-SKEW" Name="FetchUnit_bus_skew_routed.rpt"/>
<File Type="ROUTE-BUS-SKEW-PB" Name="FetchUnit_bus_skew_routed.pb"/> <File Type="ROUTE-BUS-SKEW-PB" Name="FetchUnit_bus_skew_routed.pb"/>
<File Type="ROUTE-BUS-SKEW-RPX" Name="FetchUnit_bus_skew_routed.rpx"/> <File Type="ROUTE-BUS-SKEW-RPX" Name="FetchUnit_bus_skew_routed.rpx"/>
<File Type="POSTROUTE-PHYSOPT-DCP" Name="FetchUnit_postroute_physopt.dcp"/> <File Type="POSTROUTE-PHYSOPT-DCP" Name="FetchUnit_postroute_physopt.dcp"/>
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="FetchUnit_postroute_physopt_bb.dcp"/> <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="FetchUnit_postroute_physopt_bb.dcp"/>
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="FetchUnit_timing_summary_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="FetchUnit_timing_summary_postroute_physopted.pb"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="FetchUnit_timing_summary_postroute_physopted.rpx"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="FetchUnit_bus_skew_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="FetchUnit_bus_skew_postroute_physopted.pb"/>
<File Type="BG-BIT" Name="FetchUnit.bit"/> <File Type="BG-BIT" Name="FetchUnit.bit"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="FetchUnit_bus_skew_postroute_physopted.rpx"/>
<File Type="BITSTR-RBT" Name="FetchUnit.rbt"/> <File Type="BITSTR-RBT" Name="FetchUnit.rbt"/>
<File Type="BITSTR-NKY" Name="FetchUnit.nky"/> <File Type="BITSTR-NKY" Name="FetchUnit.nky"/>
<File Type="BG-DRC" Name="FetchUnit.drc"/> <File Type="BG-DRC" Name="FetchUnit.drc"/>
@@ -66,7 +85,7 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/RegFile.v"> <File Path="$PSRCDIR/sources_1/new/ALU.v">
<FileInfo> <FileInfo>
<Attr Name="AutoDisabled" Val="1"/> <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -74,7 +93,7 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/ALU.v"> <File Path="$PSRCDIR/sources_1/new/RegFile.v">
<FileInfo> <FileInfo>
<Attr Name="AutoDisabled" Val="1"/> <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -85,7 +104,6 @@
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="FetchUnit"/> <Option Name="TopModule" Val="FetchUnit"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">

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lab2CA.runs/impl_1/opt_design.pb
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4
lab2CA.runs/impl_1/vivado.jou
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@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit) # Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Feb 16 17:35:59 2019 # Start of session at: Wed Feb 20 11:36:21 2019
# Process ID: 3548 # Process ID: 644
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1
# Command line: vivado.exe -log FetchUnit.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source FetchUnit.tcl -notrace # Command line: vivado.exe -log FetchUnit.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source FetchUnit.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit.vdi # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/FetchUnit.vdi

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lab2CA.runs/impl_1/vivado.pb
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lab2CA.runs/synth_1/FetchUnit.dcp
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4
lab2CA.runs/synth_1/FetchUnit.tcl
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@@ -17,10 +17,6 @@ proc create_report { reportName command } {
send_msg_id runtcl-5 warning "$msg" send_msg_id runtcl-5 warning "$msg"
} }
} }
set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2460-DESKTOP-8QFGS52/incrSyn
set_msg_config -id {Common 17-41} -limit 10000000
set_msg_config -id {Synth 8-256} -limit 10000
set_msg_config -id {Synth 8-638} -limit 10000
create_project -in_memory -part xc7k160tifbg484-2L create_project -in_memory -part xc7k160tifbg484-2L
set_param project.singleFileAddWarning.threshold 0 set_param project.singleFileAddWarning.threshold 0

57
lab2CA.runs/synth_1/FetchUnit.vds
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@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit) # Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Feb 16 17:27:36 2019 # Start of session at: Wed Feb 20 11:35:49 2019
# Process ID: 2948 # Process ID: 8280
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log FetchUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl # Command line: vivado.exe -log FetchUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.vds # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.vds
@@ -15,9 +15,9 @@ Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti' Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 2932 INFO: Helper process launched with PID 5464
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.449 ; gain = 101.293 Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.242 ; gain = 98.211
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
@@ -26,28 +26,30 @@ INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:53] INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:53]
WARNING: [Synth 8-350] instance 'PCAdder' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:17] WARNING: [Synth 8-350] instance 'PCAdder' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:18]
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:312] INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:312]
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:317] INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:317]
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:312] INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:312]
WARNING: [Synth 8-689] width (2) of port connection 'switch' does not match port width (1) of module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:28]
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
WARNING: [Synth 8-3331] design FetchUnit has unconnected port op_idx[1]
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.078 ; gain = 156.922 Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.078 ; gain = 156.922 Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Loading Part and Timing Information Start Loading Part and Timing Information
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Loading part: xc7k160tifbg484-2L Loading part: xc7k160tifbg484-2L
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.078 ; gain = 156.922 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
INFO: [Synth 8-5544] ROM "Dout" won't be mapped to Block RAM because address size (2) smaller than threshold (5) INFO: [Synth 8-5544] ROM "Dout" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.078 ; gain = 156.922 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.191 ; gain = 154.160
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@@ -105,8 +107,9 @@ No constraint files found.
Start Cross Boundary and Area Optimization Start Cross Boundary and Area Optimization
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met Warning: Parallel synthesis criteria is not met
WARNING: [Synth 8-3331] design FetchUnit has unconnected port op_idx[1]
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.293 ; gain = 323.137 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.582 ; gain = 320.551
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@@ -119,7 +122,7 @@ No constraint files found.
Start Timing Optimization Start Timing Optimization
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.293 ; gain = 323.137 Finished Timing Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.582 ; gain = 320.551
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@@ -131,7 +134,7 @@ Report RTL Partitions:
Start Technology Mapping Start Technology Mapping
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.293 ; gain = 323.137 Finished Technology Mapping : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 581.582 ; gain = 320.551
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@@ -155,7 +158,7 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup Finished Final Netlist Cleanup
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 Finished IO Insertion : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report Check Netlist: Report Check Netlist:
@@ -168,7 +171,7 @@ Report Check Netlist:
Start Renaming Generated Instances Start Renaming Generated Instances
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 Finished Renaming Generated Instances : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Report RTL Partitions: Report RTL Partitions:
@@ -180,25 +183,25 @@ Report RTL Partitions:
Start Rebuilding User Hierarchy Start Rebuilding User Hierarchy
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Renaming Generated Ports Start Renaming Generated Ports
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 Finished Renaming Generated Ports : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Handling Custom Attributes Start Handling Custom Attributes
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Renaming Generated Nets Start Renaming Generated Nets
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 Finished Renaming Generated Nets : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Writing Synthesis Report Start Writing Synthesis Report
@@ -234,25 +237,25 @@ Report Instance Areas:
|2 | PC |register | 29| |2 | PC |register | 29|
+------+---------+---------+------+ +------+---------+---------+------+
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 Finished Writing Synthesis Report : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. Synthesis finished with 0 errors, 0 critical warnings and 4 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
Synthesis Optimization Complete : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.293 ; gain = 323.137 Synthesis Optimization Complete : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 581.582 ; gain = 320.551
INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist
INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 680.656 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 682.250 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary: INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed. No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis INFO: [Common 17-83] Releasing license: Synthesis
19 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. 19 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully synth_design completed successfully
synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 680.656 ; gain = 430.656 synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 682.250 ; gain = 421.219
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 680.656 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 682.250 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write. WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.dcp' has been generated. INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb INFO: [runtcl-4] Executing : report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sat Feb 16 17:28:01 2019... INFO: [Common 17-206] Exiting Vivado at Wed Feb 20 11:36:14 2019...

2
lab2CA.runs/synth_1/FetchUnit_utilization_synth.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Sat Feb 16 17:28:01 2019 | Date : Wed Feb 20 11:36:14 2019
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
| Command : report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb | Command : report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb
| Design : FetchUnit | Design : FetchUnit

10
lab2CA.runs/synth_1/gen_run.xml
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@@ -1,11 +1,14 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550356053"> <GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550680547">
<File Type="PA-TCL" Name="FetchUnit.tcl"/> <File Type="PA-TCL" Name="FetchUnit.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="FetchUnit_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/> <File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
<File Type="RDS-RDS" Name="FetchUnit.vds"/> <File Type="RDS-RDS" Name="FetchUnit.vds"/>
<File Type="RDS-UTIL" Name="FetchUnit_utilization_synth.rpt"/> <File Type="RDS-UTIL" Name="FetchUnit_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="FetchUnit_utilization_synth.pb"/> <File Type="RDS-UTIL-PB" Name="FetchUnit_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="FetchUnit.dcp"/> <File Type="RDS-DCP" Name="FetchUnit.dcp"/>
<File Type="VDS-TIMINGSUMMARY" Name="FetchUnit_timing_summary_synth.rpt"/>
<File Type="VDS-TIMING-PB" Name="FetchUnit_timing_summary_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"> <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/BasicModules.v"> <File Path="$PSRCDIR/sources_1/new/BasicModules.v">
@@ -22,7 +25,7 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/RegFile.v"> <File Path="$PSRCDIR/sources_1/new/ALU.v">
<FileInfo> <FileInfo>
<Attr Name="AutoDisabled" Val="1"/> <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -30,7 +33,7 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/ALU.v"> <File Path="$PSRCDIR/sources_1/new/RegFile.v">
<FileInfo> <FileInfo>
<Attr Name="AutoDisabled" Val="1"/> <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -41,7 +44,6 @@
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="FetchUnit"/> <Option Name="TopModule" Val="FetchUnit"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">

4
lab2CA.runs/synth_1/vivado.jou
View File

@@ -2,8 +2,8 @@
# Vivado v2018.3 (64-bit) # Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Sat Feb 16 17:27:36 2019 # Start of session at: Wed Feb 20 11:35:49 2019
# Process ID: 2948 # Process ID: 8280
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log FetchUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl # Command line: vivado.exe -log FetchUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.vds # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.vds

BIN
lab2CA.runs/synth_1/vivado.pb
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Binary file not shown.

7
lab2CA.xpr
View File

@@ -66,14 +66,14 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/ALU.v"> <File Path="$PSRCDIR/sources_1/new/FetchUnit.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/FetchUnit.v"> <File Path="$PSRCDIR/sources_1/new/ALU.v">
<FileInfo> <FileInfo>
<Attr Name="AutoDisabled" Val="1"/> <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
@@ -91,8 +91,7 @@
</File> </File>
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="ALU"/> <Option Name="TopModule" Val="FetchUnit"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">