ALU now has 4 bits of it's own opcode
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@@ -1,7 +1,7 @@
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module ALU(
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module ALU(
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input wire [2:0] opcode, // NOT the same as the instruction set opcode
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input wire [3:0] opcode, // NOT the same as the instruction set opcode
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input wire [8:0] operand0,
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input wire [8:0] operand0,
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input wire [8:0] operand1,
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input wire [8:0] operand1,
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output wire [8:0] result
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output wire [8:0] result
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@@ -10,41 +10,41 @@ module ALU(
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// Wires for connecting the modules to the mux
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// Wires for connecting the modules to the mux
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wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H;
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wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H;
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// A (000) - Add
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// A (0000) - Add
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add_9bit add0(
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add_9bit add0(
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.A(operand0),
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.A(operand0),
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.B(operand1),
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.B(operand1),
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.Cin(1'b0),
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.Cin(1'b0),
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.Sum(result_A));
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.Sum(result_A));
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// B (001) - Subtract
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// B (0001) - Subtract
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sub_9bit sub0(
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sub_9bit sub0(
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.A(operand0),
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.A(operand0),
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.B(operand1),
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.B(operand1),
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.C(result_B));
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.C(result_B));
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// C (010) - OR
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// C (0010) - OR
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or_9bit or0(
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or_9bit or0(
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.A(operand0),
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.A(operand0),
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.B(operand1),
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.B(operand1),
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.C(result_C));
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.C(result_C));
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// D (011) - NOR
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// D (0011) - NOR
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nor_9bit nor0(
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nor_9bit nor0(
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.A(operand0),
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.A(operand0),
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.B(operand1),
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.B(operand1),
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.C(result_D));
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.C(result_D));
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// E (100) - AND
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// E (0100) - AND
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and_9bit and0(
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and_9bit and0(
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.A(operand0),
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.A(operand0),
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.B(operand1),
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.B(operand1),
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.C(result_E));
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.C(result_E));
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// F (101) - Shift Left
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// F (0101) - Shift Left
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shift_left sl(
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shift_left sl(
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.A(operand0),
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.A(operand0),
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.B(result_F));
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.B(result_F));
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// G (110) - Shift Logical Right
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// G (0110) - Shift Right Logical
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shift_right_logical srl(
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shift_right_logical srl(
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.A(operand0),
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.A(operand0),
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.B(result_G));
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.B(result_G));
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// H (111) //slt
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// H (0111) - Shift Right Arithmetic
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// MUX chooses which result to show based on the ALU's opcode
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// MUX chooses which result to show based on the ALU's opcode
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