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Renamed shifting for incoming shift_right_arithmetic

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This commit is contained in:
WilliamMiceli
2019-03-12 10:54:45 -04:00
parent f3ea596086
commit 9e9ff7935b
2 changed files with 9 additions and 9 deletions
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6
lab2CA.srcs/sources_1/new/ALU.v
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@@ -36,12 +36,12 @@ module ALU(
.A(operand0),
.B(operand1),
.C(result_E));
// F (101) - Shift Logical Left
shift_logical_left sll(
// F (101) - Shift Left
shift_left sl(
.A(operand0),
.B(result_F));
// G (110) - Shift Logical Right
shift_logical_right slr(
shift_right_logical srl(
.A(operand0),
.B(result_G));
// H (111) //slt

12
lab2CA.srcs/sources_1/new/BasicModules.v
View File

@@ -665,7 +665,7 @@ module register_tb();
end
endmodule
module shift_logical_left(
module shift_left(
input wire [8:0] A,
output wire [8:0] B);
@@ -674,11 +674,11 @@ module shift_logical_left(
endmodule
//testbench
module shift_logical_left_tb();
module shift_left_tb();
reg [8:0] a;
wire [8:0] b;
shift_logical_left tb0(
shift_left tb0(
.A(a),
.B(b));
@@ -702,7 +702,7 @@ module shift_logical_left_tb();
end
endmodule
module shift_logical_right(
module shift_right_logical(
input wire [8:0] A,
output wire [8:0] B);
@@ -711,11 +711,11 @@ module shift_logical_right(
endmodule
//testbench
module shift_logical_right_tb();
module shift_right_logical_tb();
reg [8:0] a;
wire [8:0] b;
shift_logical_right tb0(
shift_right_logical tb0(
.A(a),
.B(b));