Tested the instructions using the instruction memory
All of the instructions seem to be working other than beq. I might just be calling it wrong
This commit is contained in:
Johannes
BIN
lab2CA.runs/synth_1/CPU9bits.dcp
Normal file
BIN
lab2CA.runs/synth_1/CPU9bits.dcp
Normal file
Binary file not shown.
60
lab2CA.runs/synth_1/CPU9bits.tcl
Normal file
60
lab2CA.runs/synth_1/CPU9bits.tcl
Normal file
@@ -0,0 +1,60 @@
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||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
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||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
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||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
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||||
}
|
||||
}
|
||||
create_project -in_memory -part xc7k160tifbg484-2L
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|
||||
set_param project.singleFileAddWarning.threshold 0
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set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project]
|
||||
set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project]
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||||
set_property default_lib xil_defaultlib [current_project]
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||||
set_property target_language Verilog [current_project]
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||||
set_property ip_output_repo c:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project]
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||||
set_property ip_cache_permissions {read write} [current_project]
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||||
read_verilog -library xil_defaultlib {
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v
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||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v
|
||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v
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||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v
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||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v
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||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v
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||||
C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v
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||||
}
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||||
# Mark all dcp files as not used in implementation to prevent them from being
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# stitched into the results of this synthesis run. Any black boxes in the
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# design are intentionally left as such for best results. Dcp files will be
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# stitched into the design at a later time, either when this synthesis run is
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# opened, or when it is stitched into a dependent implementation run.
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foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
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set_property used_in_implementation false $dcp
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}
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set_param ips.enableIPCacheLiteLoad 1
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close [open __synthesis_is_running__ w]
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synth_design -top CPU9bits -part xc7k160tifbg484-2L
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# disable binary constraint mode for synth run checkpoints
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set_param constraints.enableBinaryConstraints false
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write_checkpoint -force -noxdef CPU9bits.dcp
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create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb"
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file delete __synthesis_is_running__
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close [open __synthesis_is_complete__ w]
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||||
494
lab2CA.runs/synth_1/CPU9bits.vds
Normal file
494
lab2CA.runs/synth_1/CPU9bits.vds
Normal file
@@ -0,0 +1,494 @@
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||||
#-----------------------------------------------------------
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||||
# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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||||
# Start of session at: Wed Mar 20 10:53:36 2019
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# Process ID: 12136
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||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
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# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
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# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
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# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
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||||
#-----------------------------------------------------------
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||||
source CPU9bits.tcl -notrace
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Command: synth_design -top CPU9bits -part xc7k160tifbg484-2L
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Starting synth_design
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||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
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||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: Launching helper process for spawning children vivado processes
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||||
INFO: Helper process launched with PID 8176
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||||
---------------------------------------------------------------------------------
|
||||
Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.945 ; gain = 102.359
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||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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||||
INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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||||
INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
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||||
WARNING: [Synth 8-567] referenced signal 'clk' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30]
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||||
WARNING: [Synth 8-567] referenced signal 'memory' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30]
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||||
WARNING: [Synth 8-567] referenced signal 'writeEnable' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30]
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WARNING: [Synth 8-567] referenced signal 'writeData' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30]
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||||
INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
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||||
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
|
||||
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
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||||
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
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||||
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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||||
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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||||
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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||||
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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||||
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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||||
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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||||
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
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||||
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342]
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||||
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
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||||
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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||||
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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||||
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
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||||
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
|
||||
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
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||||
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
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||||
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376]
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||||
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311]
|
||||
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
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||||
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
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||||
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
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||||
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
|
||||
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
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||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
|
||||
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
|
||||
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
|
||||
WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sign_extend_2bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:965]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_2bit' (25#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:965]
|
||||
WARNING: [Synth 8-689] width (3) of port connection 'A' does not match port width (2) of module 'sign_extend_2bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:89]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sign_extend_4bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1035]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_4bit' (26#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1035]
|
||||
WARNING: [Synth 8-689] width (5) of port connection 'A' does not match port width (4) of module 'sign_extend_4bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:93]
|
||||
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
|
||||
INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (27#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
|
||||
WARNING: [Synth 8-689] width (3) of port connection 'A' does not match port width (2) of module 'sign_extend_2bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:112]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (28#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
|
||||
WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0]
|
||||
WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0]
|
||||
WARNING: [Synth 8-3331] design shift_left has unconnected port A[8]
|
||||
WARNING: [Synth 8-3331] design instructionMemory has unconnected port clk
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.844 ; gain = 158.258
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.844 ; gain = 158.258
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k160tifbg484-2L
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.844 ; gain = 158.258
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
|
||||
INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[15]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[14]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[13]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[12]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[11]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[10]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[9]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[8]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[7]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[6]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[5]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[4]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[3]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[2]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[1]" won't be mapped to RAM because it is too sparse
|
||||
INFO: [Synth 8-5546] ROM "memory_reg[0]" won't be mapped to RAM because it is too sparse
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[15]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[14]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[13]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[12]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[11]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[10]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[9]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[8]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[7]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[6]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[5]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[4]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[3]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[2]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[1]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[0]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 446.785 ; gain = 189.199
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-223] decloning instance 'SE1' (sign_extend_2bit) to 'SE3'
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 144
|
||||
+---Registers :
|
||||
9 Bit Registers := 5
|
||||
+---Muxes :
|
||||
7 Input 9 Bit Muxes := 1
|
||||
2 Input 9 Bit Muxes := 22
|
||||
4 Input 9 Bit Muxes := 2
|
||||
2 Input 4 Bit Muxes := 1
|
||||
4 Input 4 Bit Muxes := 1
|
||||
15 Input 4 Bit Muxes := 1
|
||||
2 Input 3 Bit Muxes := 2
|
||||
15 Input 3 Bit Muxes := 1
|
||||
16 Input 1 Bit Muxes := 16
|
||||
2 Input 1 Bit Muxes := 17
|
||||
3 Input 1 Bit Muxes := 16
|
||||
15 Input 1 Bit Muxes := 5
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module instructionMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
7 Input 9 Bit Muxes := 1
|
||||
Module dataMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 16
|
||||
16 Input 1 Bit Muxes := 16
|
||||
2 Input 1 Bit Muxes := 16
|
||||
3 Input 1 Bit Muxes := 16
|
||||
Module decoder
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 4 Bit Muxes := 1
|
||||
4 Input 4 Bit Muxes := 1
|
||||
Module register
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
Module mux_4_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
4 Input 9 Bit Muxes := 1
|
||||
Module add_1bit
|
||||
Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 2
|
||||
Module mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 9 Bit Muxes := 1
|
||||
Module ControlUnit
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
15 Input 4 Bit Muxes := 1
|
||||
2 Input 3 Bit Muxes := 2
|
||||
15 Input 3 Bit Muxes := 1
|
||||
15 Input 1 Bit Muxes := 5
|
||||
Module bit1_mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 600 (col length:100)
|
||||
BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[8]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[7]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[6]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[5]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[4]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[3]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][8]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][7]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][6]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][5]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][4]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][3]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][8]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][7]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][6]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][5]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][4]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][3]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][8]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][7]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][6]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][5]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][4]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][3]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][8]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][7]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][6]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][5]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][4]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][3]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][8]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][7]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][6]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][5]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][4]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][3]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][8]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][7]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][6]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][5]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][4]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][3]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][8]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][7]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][6]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][5]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][4]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][3]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][8]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][7]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][6]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][5]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][4]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][3]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][8]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][7]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][6]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][5]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][4]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][3]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][8]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][7]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][6]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][5]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][4]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][3]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][2]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][1]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][0]) is unused and will be removed from module CPU9bits.
|
||||
WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[5][8]) is unused and will be removed from module CPU9bits.
|
||||
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-----+------+
|
||||
| |Cell |Count |
|
||||
+------+-----+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |LUT2 | 1|
|
||||
|3 |LUT3 | 2|
|
||||
|4 |LUT4 | 1|
|
||||
|5 |FDRE | 3|
|
||||
|6 |IBUF | 2|
|
||||
|7 |OBUF | 1|
|
||||
+------+-----+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+----------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+----------+------+
|
||||
|1 |top | | 11|
|
||||
|2 | FetchU |FetchUnit | 7|
|
||||
|3 | PC |register | 7|
|
||||
+------+---------+----------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 185 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.789 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
87 Infos, 132 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 681.789 ; gain = 431.723
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.789 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Mar 20 10:54:03 2019...
|
||||
BIN
lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
Normal file
BIN
lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb
Normal file
Binary file not shown.
179
lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt
Normal file
179
lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt
Normal file
@@ -0,0 +1,179 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Wed Mar 20 10:54:03 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
| Design : CPU9bits
|
||||
| Device : 7k160tifbg484-2L
|
||||
| Design State : Synthesized
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 2 | 0 | 101400 | <0.01 |
|
||||
| LUT as Logic | 2 | 0 | 101400 | <0.01 |
|
||||
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
|
||||
| Slice Registers | 3 | 0 | 202800 | <0.01 |
|
||||
| Register as Flip Flop | 3 | 0 | 202800 | <0.01 |
|
||||
| Register as Latch | 0 | 0 | 202800 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 3 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 325 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 650 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 600 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 3 | 0 | 285 | 1.05 |
|
||||
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 8 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 8 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 275 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 285 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 285 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
|
||||
| BUFIO | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 16 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 120 | 0.00 |
|
||||
| BUFR | 0 | 0 | 32 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 3 | Flop & Latch |
|
||||
| LUT3 | 2 | LUT |
|
||||
| IBUF | 2 | IO |
|
||||
| OBUF | 1 | IO |
|
||||
| LUT4 | 1 | LUT |
|
||||
| LUT2 | 1 | LUT |
|
||||
| BUFG | 1 | Clock |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
99
lab2CA.runs/synth_1/gen_run.xml
Normal file
99
lab2CA.runs/synth_1/gen_run.xml
Normal file
@@ -0,0 +1,99 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1553093608">
|
||||
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="CPU9bits.vds"/>
|
||||
<File Type="RDS-UTIL" Name="CPU9bits_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="CPU9bits_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="CPU9bits.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="CPU9bits_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="CPU9bits_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ControlUnit.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/FetchUnit.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/dataMemory.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/instructionMemory.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/CPU9bits.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/design_1/design_1.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="CPU9bits"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
9
lab2CA.runs/synth_1/htr.txt
Normal file
9
lab2CA.runs/synth_1/htr.txt
Normal file
@@ -0,0 +1,9 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log CPU9bits.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
12
lab2CA.runs/synth_1/vivado.jou
Normal file
12
lab2CA.runs/synth_1/vivado.jou
Normal file
@@ -0,0 +1,12 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Wed Mar 20 10:53:36 2019
|
||||
# Process ID: 12136
|
||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
|
||||
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source CPU9bits.tcl -notrace
|
||||
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