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I added a comparator, I updated the control unit so that it now uses the 4 bit ALU opcode instead of the 3 bit from before. I added testbenches to the control unit and the slt and comparator modules. However, like before I unable to run the simulation on my desktop. Finally, i added the program code for the equation solver as a test bench in the CPU9bit module
This commit is contained in:
Johannes
2019-03-12 21:14:27 -04:00
parent 3f01492398
commit cb91f6656a
29 changed files with 448 additions and 115 deletions
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6
lab2CA.runs/impl_1/gen_run.xml
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@@ -1,12 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550680547">
<File Type="PA-TCL" Name="FetchUnit.tcl"/>
<File Type="BITSTR-BMM" Name="FetchUnit_bd.bmm"/>
<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
<File Type="PA-TCL" Name="FetchUnit.tcl"/>
<File Type="OPT-DCP" Name="FetchUnit_opt.dcp"/>
<File Type="REPORTS-TCL" Name="FetchUnit_reports.tcl"/>
<File Type="OPT-HWDEF" Name="FetchUnit.hwdef"/>
<File Type="PWROPT-DCP" Name="FetchUnit_pwropt.dcp"/>
<File Type="BG-BGN" Name="FetchUnit.bgn"/>
<File Type="PWROPT-DCP" Name="FetchUnit_pwropt.dcp"/>
<File Type="PLACE-DCP" Name="FetchUnit_placed.dcp"/>
<File Type="PLACE-PRE-SIMILARITY" Name="FetchUnit_incremental_reuse_pre_placed.rpt"/>
<File Type="POSTPLACE-PWROPT-DCP" Name="FetchUnit_postplace_pwropt.dcp"/>

11
lab2CA.sim/sim_1/behav/xsim/comparator_tb.tcl Normal file
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set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns

9
lab2CA.sim/sim_1/behav/xsim/comparator_tb_vlog.prj Normal file
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@@ -0,0 +1,9 @@
# compile verilog/system verilog design source files
verilog xil_defaultlib \
"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort

8
lab2CA.sim/sim_1/behav/xsim/webtalk.jou
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@@ -2,11 +2,11 @@
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Tue Mar 12 19:46:24 2019
# Process ID: 6512
# Start of session at: Tue Mar 12 20:38:16 2019
# Process ID: 15148
# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace
source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_10344.backup.jou
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@@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Feb 20 11:30:13 2019
# Process ID: 10344
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_1408.backup.jou
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@@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Feb 27 11:43:09 2019
# Process ID: 1408
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_14864.backup.jou
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@@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Feb 27 11:39:16 2019
# Process ID: 14864
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_16620.backup.jou
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@@ -1,12 +0,0 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Thu Feb 21 14:46:02 2019
# Process ID: 16620
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/fetchUnit_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/REPOSITORIES/Educational/Western -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_18368.backup.jou Normal file
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@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Tue Mar 12 19:51:55 2019
# Process ID: 18368
# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_5116.backup.jou Normal file
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@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Tue Mar 12 19:52:36 2019
# Process ID: 5116
# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_6512.backup.jou Normal file
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@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Tue Mar 12 19:46:24 2019
# Process ID: 6512
# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace

12
lab2CA.sim/sim_1/behav/xsim/webtalk_7548.backup.jou Normal file
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@@ -0,0 +1,12 @@
#-----------------------------------------------------------
# Webtalk v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Tue Mar 12 20:36:54 2019
# Process ID: 7548
# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim
# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace
# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log
# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou
#-----------------------------------------------------------
source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/xsim_webtalk.tcl -notrace

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lab2CA.sim/sim_1/behav/xsim/xelab.pb
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2
lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/Compile_Options.txt
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@@ -1 +1 @@
-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "add9bit_tb_behav" "xil_defaultlib.add9bit_tb" "xil_defaultlib.glbl" -log "elaborate.log"
-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "add9bit_tb_behav" "xil_defaultlib.add9bit_tb" "xil_defaultlib.glbl" -log "elaborate.log"

17
lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml
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@@ -1,16 +1,16 @@
<?xml version="1.0" encoding="UTF-8" ?>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Sat Feb 16 14:04:46 2019'>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Tue Mar 12 19:52:36 2019'>
<section name="__ROOT__" level="0" order="1" description="">
<section name="software_version_and_target_device" level="1" order="1" description="">
<keyValuePair key="beta" value="FALSE" description="" />
<keyValuePair key="build_version" value="2405991" description="" />
<keyValuePair key="date_generated" value="Sat Feb 16 14:04:45 2019" description="" />
<keyValuePair key="date_generated" value="Tue Mar 12 19:52:35 2019" description="" />
<keyValuePair key="os_platform" value="WIN64" description="" />
<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
<keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" />
<keyValuePair key="project_iteration" value="2" description="" />
<keyValuePair key="random_id" value="4e917e26-7591-4435-9135-15bd446b0238" description="" />
<keyValuePair key="registration_id" value="174150793_174150794_210688225_140" description="" />
<keyValuePair key="random_id" value="fe5d421c9f2b5ebc958da28a6d468b09" description="" />
<keyValuePair key="registration_id" value="fe5d421c9f2b5ebc958da28a6d468b09" description="" />
<keyValuePair key="route_design" value="FALSE" description="" />
<keyValuePair key="target_device" value="not_applicable" description="" />
<keyValuePair key="target_family" value="not_applicable" description="" />
@@ -19,11 +19,11 @@
<keyValuePair key="tool_flow" value="xsim_vivado" description="" />
</section>
<section name="user_environment" level="1" order="2" description="">
<keyValuePair key="cpu_name" value="Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" description="" />
<keyValuePair key="cpu_name" value="Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz" description="" />
<keyValuePair key="cpu_speed" value="3492 MHz" description="" />
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
<keyValuePair key="system_ram" value="34.000 GB" description="" />
<keyValuePair key="system_ram" value="17.000 GB" description="" />
<keyValuePair key="total_processors" value="1" description="" />
</section>
<section name="vivado_usage" level="1" order="3" description="">
@@ -35,9 +35,8 @@
<section name="usage" level="2" order="2" description="">
<keyValuePair key="iteration" value="0" description="" />
<keyValuePair key="runtime" value="1 us" description="" />
<keyValuePair key="simulation_memory" value="6616_KB" description="" />
<keyValuePair key="simulation_time" value="0.08_sec" description="" />
<keyValuePair key="trace_waveform" value="true" description="" />
<keyValuePair key="simulation_memory" value="5920_KB" description="" />
<keyValuePair key="simulation_time" value="0.01_sec" description="" />
</section>
</section>
</section>

31
lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/xsim_webtalk.tcl Normal file
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webtalk_init -webtalk_dir C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Tue Mar 12 19:53:25 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "fe5d421c9f2b5ebc958da28a6d468b09" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.09_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "5696_KB" -context "xsim\\usage"
webtalk_transmit -clientid 3522894383 -regid "" -xml C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

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lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/xsim.mem
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1
lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/Compile_Options.txt Normal file
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@@ -0,0 +1 @@
-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "comparator_tb_behav" "xil_defaultlib.comparator_tb" "xil_defaultlib.glbl" -log "elaborate.log"

1
lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/TempBreakPointFile.txt Normal file
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@@ -0,0 +1 @@
Breakpoint File Version 1.0

107
lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/obj/xsim_1.c Normal file
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@@ -0,0 +1,107 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
extern void execute_3(char*, char *);
extern void execute_9(char*, char *);
extern void execute_10(char*, char *);
extern void execute_8(char*, char *);
extern void execute_5(char*, char *);
extern void execute_6(char*, char *);
extern void execute_7(char*, char *);
extern void execute_11(char*, char *);
extern void execute_12(char*, char *);
extern void execute_13(char*, char *);
extern void execute_14(char*, char *);
extern void execute_15(char*, char *);
extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[13] = {(funcp)execute_3, (funcp)execute_9, (funcp)execute_10, (funcp)execute_8, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)vlog_transfunc_eventcallback};
const int NumRelocateId= 13;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/comparator_tb_behav/xsim.reloc", (void **)funcTab, 13);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/comparator_tb_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/comparator_tb_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern void implicit_HDL_SCinstatiate();
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_sv_type_file_path_name("xsim.dir/comparator_tb_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/comparator_tb_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/comparator_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

43
lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/webtalk/usage_statistics_ext_xsim.xml Normal file
View File

@@ -0,0 +1,43 @@
<?xml version="1.0" encoding="UTF-8" ?>
<webTalkData fileName='usage_statistics_ext_xsim.xml' majorVersion='1' minorVersion='0' timeStamp='Tue Mar 12 20:38:16 2019'>
<section name="__ROOT__" level="0" order="1" description="">
<section name="software_version_and_target_device" level="1" order="1" description="">
<keyValuePair key="beta" value="FALSE" description="" />
<keyValuePair key="build_version" value="2405991" description="" />
<keyValuePair key="date_generated" value="Tue Mar 12 20:38:15 2019" description="" />
<keyValuePair key="os_platform" value="WIN64" description="" />
<keyValuePair key="product_version" value="XSIM v2018.3 (64-bit)" description="" />
<keyValuePair key="project_id" value="0a5803efda44405bb28bbf43ba22e808" description="" />
<keyValuePair key="project_iteration" value="2" description="" />
<keyValuePair key="random_id" value="fe5d421c9f2b5ebc958da28a6d468b09" description="" />
<keyValuePair key="registration_id" value="fe5d421c9f2b5ebc958da28a6d468b09" description="" />
<keyValuePair key="route_design" value="FALSE" description="" />
<keyValuePair key="target_device" value="not_applicable" description="" />
<keyValuePair key="target_family" value="not_applicable" description="" />
<keyValuePair key="target_package" value="not_applicable" description="" />
<keyValuePair key="target_speed" value="not_applicable" description="" />
<keyValuePair key="tool_flow" value="xsim_vivado" description="" />
</section>
<section name="user_environment" level="1" order="2" description="">
<keyValuePair key="cpu_name" value="Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz" description="" />
<keyValuePair key="cpu_speed" value="3492 MHz" description="" />
<keyValuePair key="os_name" value="Microsoft Windows 8 or later , 64-bit" description="" />
<keyValuePair key="os_release" value="major release (build 9200)" description="" />
<keyValuePair key="system_ram" value="17.000 GB" description="" />
<keyValuePair key="total_processors" value="1" description="" />
</section>
<section name="vivado_usage" level="1" order="3" description="">
</section>
<section name="xsim" level="1" order="4" description="">
<section name="command_line_options" level="2" order="1" description="">
<keyValuePair key="command" value="xsim" description="" />
</section>
<section name="usage" level="2" order="2" description="">
<keyValuePair key="iteration" value="0" description="" />
<keyValuePair key="runtime" value="30 ns" description="" />
<keyValuePair key="simulation_memory" value="5900_KB" description="" />
<keyValuePair key="simulation_time" value="0.01_sec" description="" />
</section>
</section>
</section>
</webTalkData>

BIN
lab2CA.sim/sim_1/behav/xsim/xsim.dir/comparator_tb_behav/xsim.mem Normal file
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27
lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl
View File

@@ -1,6 +1,6 @@
webtalk_init -webtalk_dir C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Tue Mar 12 19:48:08 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key date_generated -value "Tue Mar 12 19:52:40 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
@@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "fe5d421c9f2b5ebc958da28a6d468b09" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "5" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "8" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz" -context "user_environment"
@@ -22,21 +22,10 @@ webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment"
webtalk_register_client -client xsim
webtalk_add_data -client xsim -key File_Counter -value "2" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key Simulation_Image_Code -value "65 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Image_Data -value "2 KB" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Processes -value "17" -context "xsim\\usage"
webtalk_add_data -client xsim -key Total_Instances -value "3" -context "xsim\\usage"
webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Time -value "0.62_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Compiler_Memory -value "36408_KB" -context "xsim\\usage"
webtalk_transmit -clientid 1095157529 -regid "" -xml C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
webtalk_add_data -client xsim -key runtime -value "40 ns" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.01_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "5472_KB" -context "xsim\\usage"
webtalk_transmit -clientid 3382459669 -regid "" -xml C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

BIN
lab2CA.sim/sim_1/behav/xsim/xvlog.pb
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4
lab2CA.srcs/sources_1/new/ALU.v
View File

@@ -53,6 +53,10 @@ module ALU(
.A(operand0),
.B(result_I));
// J (1001)
slt slt0(
.inA(operand0),
.inB(operand1),
.outA(result));
// K (1010)
// L (1011)
// M (1100)

55
lab2CA.srcs/sources_1/new/BasicModules.v
View File

@@ -215,6 +215,49 @@ module and9bit_tb();
end
endmodule
module comparator (
input wire [8:0] A,
input wire [8:0] B,
output wire [8:0] C);
assign C = (~A & ~B) | (A & B);
endmodule
//testbench
module comparator_tb();
reg [8:0] a,b;
wire [8:0] c;
comparator comparator0(
.A(a),
.B(b),
.C(c));
initial begin
a = 9'b000000000;
b = 9'b000000000;
#5
a = 9'b000000000;
b = 9'b000000001;
#5
a = 9'b000000001;
b = 9'b000000000;
#5
a = 9'b000000001;
b = 9'b000000001;
#5
a = 9'b000100001;
b = 9'b000000001;
#5
a = 9'b000100001;
b = 9'b000100001;
#5
$finish;
end
endmodule
module decoder (
input wire en,
input wire [1:0] index,
@@ -887,36 +930,30 @@ endmodule
module slt (
input wire en,
input wire [8:0] inA, inB,
output reg outA);
output reg [8:0] outA);
always @(inA, inB)begin
if (inA < inB) begin
outA = 1;
outA = 9'b000000001;
end
else begin
outA = 0;
outA = 9'b000000000;
end
end
endmodule
//testbench
module slt_tb();
reg enable;
reg [8:0] indexA;
reg [8:0] indexB;
wire outputA;
slt slt0(
.en(enable),
.inA(indexA),
.inB(indexB),
.outA(outputA));
initial begin
enable = 0;
#5
enable = 1;
#5
indexA = 9'b000000000;
indexB = 9'b000000000;
#10

40
lab2CA.srcs/sources_1/new/CPU9bits.v
View File

@@ -89,3 +89,43 @@ module CPU9bits(input wire [8:0] instr,
endmodule
module CPU9bits_tb();
reg [8:0] instruction;
reg clk, reset;
wire done;
initial begin
clk = 1'b0;
end
always begin
#5 clk = ~clk; // Period to be determined
end
CPU9bits CPU9bits0(
.instr(instruction),
.reset(reset),
.clk(clk),
.done(done));
initial begin
reset = 0;
#10
reset = 1;
#10
instruction = 000100000;
#10
instruction = 000101001;
#10
instruction = 010100010;
#10
instruction = 111100000;
#10
instruction = 111100000;
#10
instruction = 000000000;
#10
$finish;
end
endmodule

101
lab2CA.srcs/sources_1/new/ControlUnit.v
View File

@@ -3,72 +3,133 @@
module ControlUnit(
input wire [3:0] instIn,
input wire functBit,
output reg [2:0] aluOut,
output reg [3:0] aluOut,
output reg [2:0] FU,
output reg addi,
output reg mem,
output reg load,
output reg RegEn
);
output reg RegEn);
always @(instIn)begin
case(instIn)
4'b0101:
if(functBit == 1) begin
aluOut <= 3'b001; //sub
aluOut <= 4'b0001; //sub
RegEn <= 1'b0;
end
else begin
aluOut <= 3'b000; //Add
aluOut <= 4'b0000; //Add
RegEn <= 1'b0;
end
4'b0111: begin
aluOut <= 3'b111; //nor
4'b1101: begin
aluOut <= 4'b0011; //nor
RegEn <= 1'b0;
end
4'b1110:
if(functBit == 1) begin
aluOut <= 3'b100; //and
aluOut <= 4'b0100; //and
RegEn <= 1'b0;
end
else begin
aluOut <= 3'b010; //or
aluOut <= 4'b0010; //or
RegEn <= 1'b0;
end
4'b1111:
if(functBit == 1) begin
aluOut <= 3'b110; //srl
aluOut <= 4'b0110; //srl
RegEn <= 1'b0;
end
else begin
aluOut <= 3'b101; //sll
aluOut <= 4'b0101; //shift left
RegEn <= 1'b0;
end
4'b0111: begin
aluOut <= 4'b1001; //slt
RegEn <= 1'b0;
end
4'b0110: begin
addi <= 1'b1; // addi
RegEn <= 1'b0;
end
end
4'b1001: begin
FU <= 3'b010; // jump
RegEn <= 1'b1;
end
end
4'b1100: begin
FU <= 3'b011; // branch
RegEn <= 1'b1;
end
end
4'b1000: begin
FU <= 3'b001; // jumpreg
RegEn <= 1'b1;
end
end
4'b0001: begin
mem <= 1'b0; // load
RegEn <= 1'b0;
end
end
4'b0010: begin
mem <= 1'b1; // store
RegEn <= 1'b1;
end
default: aluOut <= 3'bxxxx;
end
default: aluOut <= 4'bxxxx;
endcase
end
endmodule
end
endmodule
module ControlUnit_tb();
reg [3:0] instruction;
reg functionB;
wire [3:0] aluOutput;
wire [2:0] FetchUnit;
wire addImmediate;
wire memory;
wire loadIt;
wire RegEnable;
ControlUnit ControlUnit0(
.instIn(instruction),
.functBit(functionB),
.aluOut(aluOutput),
.FU(FetchUnit),
.addi(addImmediate),
.mem(memory),
.load(loadIt),
.RegEn(RegEnable)
);
initial begin
functionB = 1'b0;
instruction = 4'b0101;
#5
functionB = 1'b1;
#5
functionB = 1'b0;
instruction = 4'b1110;
#5
functionB = 1'b1;
#5
functionB = 1'b0;
instruction = 4'b1111;
#5
functionB = 1'b1;
#5
instruction = 4'b0111;
#5
instruction = 4'b0110;
#5
instruction = 4'b1001;
#5
instruction = 4'b1100;
#5
instruction = 4'b1000;
#5
instruction = 4'b0001;
#5
instruction = 4'b0010;
#5
$finish;
end
endmodule

4
lab2CA.xpr
View File

@@ -31,7 +31,7 @@
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="75"/>
<Option Name="WTXSimLaunchSim" Val="80"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -129,7 +129,7 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="slt_tb"/>
<Option Name="TopModule" Val="comparator_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>