Aded list of things to fix

This commit is contained in:
WilliamMiceli
2019-03-25 18:04:44 -04:00
parent 97fcfb7ef1
commit ce86652a00

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@@ -1,5 +1,10 @@
# ECE 3570 Lab # ECE 3570 Lab
## Unknown Status of Fixes ## Things to fix
* Only two registers are being written to, first two within simulation is not being written to * Make RAM write edge-triggered only
* RTL_RAM is what it needs to be showing as, since VIvado will recognize it as such
* Make ROM asyncronous (can be read at any time)
* RTL_ROM is what it needs to be showing as, since VIvado will recognize it as such
* Get rid of if statememnts in RAM and ROM
* Get programs working properly