ALU opcode is different from instruction opcode, so reducing to needed operations only

This commit is contained in:
WilliamMiceli
2019-02-15 17:02:54 -05:00
parent 582c80998e
commit d6cee0483c

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@@ -1,25 +1,27 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module ALU( module ALU(
input wire [3:0] opcode, input wire [2:0] opcode,
input wire [8:0] operand0, input wire [8:0] operand0,
input wire [8:0] operand1, input wire [8:0] operand1,
output wire [8:0] result output wire [8:0] result
); );
// Wires for connecting the modules to the mux // Wires for connecting the modules to the mux
wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P; wire [8:0] A,B,C,D,E,F,G,H;
// Please place modules in order of OPCODE, to make them easier to find
// A (000) - Add
// B (001) - Subtract
// C (010) - OR
// D (011) - NOR
// E (100) - AND
// F (101) - Shift Logical Left
// G (110) - Shift Logical Right
// H (111)
// MUX chooses which result to show based on the OPCODE // MUX chooses which result to show based on the OPCODE
mux_16_1 mux_result( mux_8_1 mux_result(
.switch(opcode), .switch(opcode),
.A(A), .A(A),
.B(B), .B(B),
@@ -29,14 +31,6 @@ module ALU(
.F(F), .F(F),
.G(G), .G(G),
.H(H), .H(H),
.I(I),
.J(J),
.K(K),
.L(L),
.M(M),
.N(N),
.O(O),
.P(P),
.out(result)); .out(result));
endmodule endmodule