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Fixed unconnected wires

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WilliamMiceli
2019-03-29 17:21:29 -04:00
parent db8ceeefb5
commit d8c7031e1b
1 changed files with 5 additions and 5 deletions
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10
lab2CA.srcs/sources_1/new/ALU.v
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@@ -10,8 +10,8 @@ module ALU(
// Wires for connecting the modules to the mux // Wires for connecting the modules to the mux
wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H,result_I,result_J,result_K,result_L,result_M,result_N,result_O,result_P; wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H,result_I,result_J,result_K,result_L,result_M,result_N,result_O,result_P;
wire cout; wire cout;
// A (0000) - Add
// A (0000) - Add
add_9bit add0( add_9bit add0(
.A(operand0), .A(operand0),
.B(operand1), .B(operand1),
@@ -41,15 +41,15 @@ module ALU(
.C(result_E)); .C(result_E));
// F (0101) - Shift Left // F (0101) - Shift Left
shift_left sl( shift_left sl(
.A(operand0), .A(operand0[7:0]),
.B(result_F)); .B(result_F));
// G (0110) - Shift Right Logical // G (0110) - Shift Right Logical
shift_right_logical srl( shift_right_logical srl(
.A(operand0), .A(operand0[8:1]),
.B(result_G)); .B(result_G));
// H (0111) - Shift Right Arithmetic // H (0111) - Shift Right Arithmetic
shift_right_arithmetic sra( shift_right_arithmetic sra(
.A(operand0), .A(operand0[8:1]),
.B(result_H)); .B(result_H));
// I (1000) - NOT // I (1000) - NOT
not_9bit not0( not_9bit not0(