Minor changes to CPU

2019-03-16 14:55:37 -04:00
parent fa5caec5dd
commit e8554a5a9a
3 changed files with 4 additions and 4 deletions
--- a/lab2CA.srcs/sources_1/new/dataMemory.v
+++ b/lab2CA.srcs/sources_1/new/dataMemory.v
@@ -27,10 +27,10 @@ module dataMemory(
        memory[15] <= 9'b000000000;
    end

-    always@(address, posedge clk)begin
+    always@(address)begin
        if(clk == 1'b1)begin
        readData <= memory[address];
-        if(writeEnable == 1'b1)begin
+        if(writeEnable == 1'b0)begin
        memory[address] <= writeData;
        end
        else begin