Minor changes to CPU

2019-03-16 14:55:37 -04:00
parent fa5caec5dd
commit e8554a5a9a
3 changed files with 4 additions and 4 deletions
--- a/lab2CA.srcs/sources_1/new/instructionMemory.v
+++ b/lab2CA.srcs/sources_1/new/instructionMemory.v
@@ -19,7 +19,7 @@ module instructionMemory(
    end
    
    
-    always@(address, posedge clk)begin
+    always@(address)begin
        readData <= memory[address];
    end
 endmodule