William/WMU-ECE-3570-Lab
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Minor changes to CPU

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This commit is contained in:
Johannes
2019-03-16 14:55:37 -04:00
parent fa5caec5dd
commit e8554a5a9a
3 changed files with 4 additions and 4 deletions
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2
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -20,7 +20,7 @@ module CPU9bits(
.clk(clk), .clk(clk),
.writeEnable(loadS), .writeEnable(loadS),
.writeData(op0), .writeData(op0),
.address(AluOut), .address(op1),
.readData(dataMemOut) .readData(dataMemOut)
); );

4
lab2CA.srcs/sources_1/new/dataMemory.v
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@@ -27,10 +27,10 @@ module dataMemory(
memory[15] <= 9'b000000000; memory[15] <= 9'b000000000;
end end
always@(address, posedge clk)begin always@(address)begin
if(clk == 1'b1)begin if(clk == 1'b1)begin
readData <= memory[address]; readData <= memory[address];
if(writeEnable == 1'b1)begin if(writeEnable == 1'b0)begin
memory[address] <= writeData; memory[address] <= writeData;
end end
else begin else begin

2
lab2CA.srcs/sources_1/new/instructionMemory.v
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@@ -19,7 +19,7 @@ module instructionMemory(
end end
always@(address, posedge clk)begin always@(address)begin
readData <= memory[address]; readData <= memory[address];
end end
endmodule endmodule