Vivado stuff
This commit is contained in:
WilliamMiceli
Binary file not shown.
@@ -17,32 +17,30 @@ proc create_report { reportName command } {
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send_msg_id runtcl-5 warning "$msg"
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}
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}
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set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-10176-DESKTOP-8QFGS52/incrSyn
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set_msg_config -id {Synth 8-256} -limit 10000
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set_msg_config -id {Synth 8-638} -limit 10000
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set_msg_config -id {Vivado 12-818} -string {{WARNING: [Vivado 12-818] No files matched 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/Bank_behav1.wcfg'}} -suppress
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create_project -in_memory -part xc7k160tifbg484-2L
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set_param project.singleFileAddWarning.threshold 0
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set_param project.compositeFile.enableAutoGeneration 0
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set_param synth.vivado.isSynthRun true
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set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project]
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set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project]
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set_property webtalk.parent_dir {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/wt} [current_project]
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set_property parent.project_path {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr} [current_project]
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set_property default_lib xil_defaultlib [current_project]
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set_property target_language Verilog [current_project]
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set_property ip_output_repo c:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project]
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set_property ip_output_repo {c:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/ip} [current_project]
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set_property ip_cache_permissions {read write} [current_project]
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read_verilog -library xil_defaultlib {
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v
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C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v
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{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v}
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{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v}
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{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v}
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{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v}
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{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v}
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{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v}
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{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v}
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{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v}
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{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v}
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{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v}
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{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v}
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}
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# Mark all dcp files as not used in implementation to prevent them from being
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# stitched into the results of this synthesis run. Any black boxes in the
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@@ -2,12 +2,12 @@
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Sat Apr 6 17:33:19 2019
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# Process ID: 7092
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# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
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# Start of session at: Wed Apr 10 12:49:25 2019
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# Process ID: 13540
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# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
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# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
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# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
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# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
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# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
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# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
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#-----------------------------------------------------------
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source CPU9bits.tcl -notrace
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Command: synth_design -top CPU9bits -part xc7k160tifbg484-2L
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@@ -15,106 +15,102 @@ Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 7732
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INFO: Helper process launched with PID 17664
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---------------------------------------------------------------------------------
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Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.789 ; gain = 101.883
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Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 362.465 ; gain = 101.664
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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INFO: [Synth 8-6157] synthesizing module 'FDModule' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
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INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:773]
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INFO: [Synth 8-6155] done synthesizing module 'register' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:773]
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INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
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INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:332]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:338]
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INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:332]
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INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (6#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
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WARNING: [Synth 8-567] referenced signal 'En' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:266]
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INFO: [Synth 8-6155] done synthesizing module 'decoder' (7#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
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INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:403]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:408]
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INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (8#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:403]
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INFO: [Synth 8-6155] done synthesizing module 'RegFile' (9#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:13]
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INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (10#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'FDModule' (11#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
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INFO: [Synth 8-6157] synthesizing module 'fDPipReg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:849]
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INFO: [Synth 8-6155] done synthesizing module 'fDPipReg' (12#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:849]
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INFO: [Synth 8-6157] synthesizing module 'EMModule' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v:5]
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INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (13#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1341]
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INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1406]
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INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:683]
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INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (14#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:683]
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INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (15#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1406]
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INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (16#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1341]
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INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:720]
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INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (17#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:720]
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INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:639]
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INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (18#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:639]
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INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
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INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (19#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
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INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:883]
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INFO: [Synth 8-6155] done synthesizing module 'shift_left' (20#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:883]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:957]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (21#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:957]
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INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:920]
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INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (22#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:920]
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INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
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INFO: [Synth 8-6155] done synthesizing module 'less_than' (23#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
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INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1455]
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INFO: [Synth 8-6155] done synthesizing module 'BEQ' (24#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1455]
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INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:531]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:537]
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INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (25#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:531]
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INFO: [Synth 8-6155] done synthesizing module 'ALU' (26#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
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INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (27#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
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INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:346]
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INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:352]
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INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (28#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:346]
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INFO: [Synth 8-6155] done synthesizing module 'EMModule' (29#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v:5]
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INFO: [Synth 8-6157] synthesizing module 'eMPipReg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:866]
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INFO: [Synth 8-6155] done synthesizing module 'eMPipReg' (30#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:866]
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WARNING: [Synth 8-689] width (62) of port connection 'Din' does not match port width (61) of module 'eMPipReg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:49]
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WARNING: [Synth 8-689] width (62) of port connection 'Dout' does not match port width (61) of module 'eMPipReg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:50]
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INFO: [Synth 8-6157] synthesizing module 'WMUdule' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'WMUdule' (31#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (32#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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WARNING: [Synth 8-3331] design WMUdule has unconnected port reset
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WARNING: [Synth 8-3331] design WMUdule has unconnected port clk
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INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
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INFO: [Synth 8-6157] synthesizing module 'FDModule' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
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INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3]
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INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
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INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:773]
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INFO: [Synth 8-6155] done synthesizing module 'register' (2#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:773]
|
||||
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
|
||||
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (3#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:332]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:338]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:332]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (6#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'decoder' (7#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:403]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:408]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (8#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:403]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:14]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (10#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'FDModule' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FDModule.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'fDPipReg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:849]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'fDPipReg' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:849]
|
||||
INFO: [Synth 8-6157] synthesizing module 'EMModule' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v:5]
|
||||
INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1341]
|
||||
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1406]
|
||||
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:683]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:683]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1406]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (16#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1341]
|
||||
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:720]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:720]
|
||||
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:639]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:639]
|
||||
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:883]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:883]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:957]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:957]
|
||||
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:920]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:920]
|
||||
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'less_than' (23#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316]
|
||||
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1455]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (24#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1455]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:531]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:537]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:531]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'ALU' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
|
||||
INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (27#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1026]
|
||||
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:346]
|
||||
INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:352]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (28#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:346]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'EMModule' (29#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/EMModule.v:5]
|
||||
INFO: [Synth 8-6157] synthesizing module 'eMPipReg' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:866]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'eMPipReg' (30#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:866]
|
||||
INFO: [Synth 8-6157] synthesizing module 'WMUdule' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'WMUdule' (31#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/WMUdule.v:3]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (32#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
|
||||
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[8]
|
||||
WARNING: [Synth 8-3331] design dataMemory has unconnected port address[7]
|
||||
WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[50]
|
||||
WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[49]
|
||||
WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[48]
|
||||
WARNING: [Synth 8-3331] design EMModule has unconnected port PipIn[47]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.430 ; gain = 158.523
|
||||
Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.434 ; gain = 157.633
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.430 ; gain = 158.523
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 418.434 ; gain = 157.633
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k160tifbg484-2L
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.430 ; gain = 158.523
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 418.434 ; gain = 157.633
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
|
||||
INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 416.430 ; gain = 158.523
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 418.434 ; gain = 157.633
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-223] decloning instance 'EM/SE1' (sign_extend_3bit) to 'EM/SE3'
|
||||
|
||||
@@ -131,13 +127,12 @@ Detailed RTL Component Info :
|
||||
+---XORs :
|
||||
2 Input 1 Bit XORs := 162
|
||||
+---Registers :
|
||||
61 Bit Registers := 1
|
||||
62 Bit Registers := 1
|
||||
51 Bit Registers := 1
|
||||
9 Bit Registers := 10
|
||||
+---RAMs :
|
||||
4K Bit RAMs := 1
|
||||
909 Bit RAMs := 1
|
||||
+---Muxes :
|
||||
7 Input 9 Bit Muxes := 1
|
||||
2 Input 9 Bit Muxes := 8
|
||||
4 Input 9 Bit Muxes := 4
|
||||
2 Input 4 Bit Muxes := 2
|
||||
@@ -155,10 +150,6 @@ Finished RTL Component Statistics
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module instructionMemory
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
7 Input 9 Bit Muxes := 1
|
||||
Module register
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
@@ -197,7 +188,7 @@ Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
9 Bit Registers := 1
|
||||
+---RAMs :
|
||||
4K Bit RAMs := 1
|
||||
909 Bit RAMs := 1
|
||||
Module bit1_mux_2_1
|
||||
Detailed RTL Component Info :
|
||||
+---Muxes :
|
||||
@@ -205,7 +196,7 @@ Detailed RTL Component Info :
|
||||
Module eMPipReg
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
61 Bit Registers := 1
|
||||
62 Bit Registers := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
@@ -223,33 +214,27 @@ No constraint files found.
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[46]' (FDRE) to 'pipe1/Dout_reg[44]'
|
||||
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[50]' (FDRE) to 'pipe1/Dout_reg[17]'
|
||||
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[48]' (FDRE) to 'pipe1/Dout_reg[17]'
|
||||
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[42]' (FDRE) to 'pipe1/Dout_reg[44]'
|
||||
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[44]' (FDRE) to 'pipe1/Dout_reg[0]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[0] )
|
||||
INFO: [Synth 8-3886] merging instance 'pipe2/Dout_reg[4]' (FDRE) to 'pipe2/Dout_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[10]' (FDRE) to 'pipe1/Dout_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[4]' (FDRE) to 'pipe1/Dout_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[9]' (FDRE) to 'pipe1/Dout_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[14]' (FDRE) to 'pipe1/Dout_reg[11]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[11] )
|
||||
INFO: [Synth 8-3886] merging instance 'pipe2/Dout_reg[1]' (FDRE) to 'pipe2/Dout_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'pipe2/Dout_reg[2]' (FDRE) to 'pipe1/Dout_reg[11]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[11] )
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 585.000 ; gain = 327.094
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 594.785 ; gain = 333.984
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
ROM:
|
||||
+------------------+------------+---------------+----------------+
|
||||
|Module Name | RTL Object | Depth x Width | Implemented As |
|
||||
+------------------+------------+---------------+----------------+
|
||||
|instructionMemory | p_0_out | 64x9 | LUT |
|
||||
|CPU9bits | p_0_out | 64x9 | LUT |
|
||||
+------------------+------------+---------------+----------------+
|
||||
|
||||
|
||||
Block RAM: Preliminary Mapping Report (see note below)
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|dataMemory: | memory_reg | 512 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
|
||||
|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|
||||
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
|
||||
@@ -267,7 +252,7 @@ No constraint files found.
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 585.000 ; gain = 327.094
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 594.785 ; gain = 333.984
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP and Shift Register Reporting
|
||||
@@ -277,7 +262,7 @@ Block RAM: Final Mapping Report
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|dataMemory: | memory_reg | 512 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
|
||||
|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 |
|
||||
+------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
@@ -292,12 +277,8 @@ Report RTL Partitions:
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[3]' (FDRE) to 'pipe1/Dout_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[5]' (FDRE) to 'pipe1/Dout_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'pipe1/Dout_reg[8]' (FDRE) to 'pipe1/Dout_reg[6]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\pipe1/Dout_reg[6] )
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 585.000 ; gain = 327.094
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 594.785 ; gain = 333.984
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -321,7 +302,7 @@ Start Final Netlist Cleanup
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
@@ -334,7 +315,7 @@ Report Check Netlist:
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -346,25 +327,25 @@ Report RTL Partitions:
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
@@ -381,59 +362,67 @@ Report Cell Usage:
|
||||
| |Cell |Count |
|
||||
+------+---------+------+
|
||||
|1 |BUFG | 1|
|
||||
|2 |LUT1 | 1|
|
||||
|3 |LUT2 | 6|
|
||||
|4 |LUT3 | 17|
|
||||
|5 |LUT4 | 23|
|
||||
|6 |LUT5 | 11|
|
||||
|7 |LUT6 | 9|
|
||||
|2 |LUT1 | 2|
|
||||
|3 |LUT2 | 9|
|
||||
|4 |LUT3 | 22|
|
||||
|5 |LUT4 | 25|
|
||||
|6 |LUT5 | 42|
|
||||
|7 |LUT6 | 101|
|
||||
|8 |MUXF7 | 1|
|
||||
|9 |RAMB18E1 | 1|
|
||||
|10 |FDRE | 58|
|
||||
|10 |FDRE | 181|
|
||||
|11 |IBUF | 2|
|
||||
|12 |OBUF | 10|
|
||||
+------+---------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+-----------+-----------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+-----------+-----------+------+
|
||||
|1 |top | | 140|
|
||||
|2 | EM |EMModule | 1|
|
||||
|3 | dM |dataMemory | 1|
|
||||
|4 | FD |FDModule | 46|
|
||||
|5 | FetchU |FetchUnit | 10|
|
||||
|6 | PC |register_1 | 10|
|
||||
|7 | RF |RegFile | 36|
|
||||
|8 | r0 |register | 18|
|
||||
|9 | r1 |register_0 | 18|
|
||||
|10 | W |WMUdule | 9|
|
||||
|11 | mux5 |mux_2_1 | 9|
|
||||
|12 | pipe1 |fDPipReg | 55|
|
||||
|13 | pipe2 |eMPipReg | 16|
|
||||
+------+-----------+-----------+------+
|
||||
+------+-----------+------------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+-----------+------------+------+
|
||||
|1 |top | | 397|
|
||||
|2 | EM |EMModule | 46|
|
||||
|3 | Bank |RegFile_4 | 45|
|
||||
|4 | r0 |register_5 | 17|
|
||||
|5 | r1 |register_6 | 10|
|
||||
|6 | r2 |register_7 | 9|
|
||||
|7 | r3 |register_8 | 9|
|
||||
|8 | dM |dataMemory | 1|
|
||||
|9 | FD |FDModule | 105|
|
||||
|10 | CU |ControlUnit | 9|
|
||||
|11 | FetchU |FetchUnit | 42|
|
||||
|12 | PC |register_3 | 42|
|
||||
|13 | RF |RegFile | 54|
|
||||
|14 | r0 |register | 9|
|
||||
|15 | r1 |register_0 | 27|
|
||||
|16 | r2 |register_1 | 9|
|
||||
|17 | r3 |register_2 | 9|
|
||||
|18 | W |WMUdule | 18|
|
||||
|19 | mux5 |mux_2_1 | 18|
|
||||
|20 | pipe1 |fDPipReg | 154|
|
||||
|21 | pipe2 |eMPipReg | 61|
|
||||
+------+-----------+------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 9 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 585.000 ; gain = 327.094
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 6 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 594.785 ; gain = 333.984
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 682.445 ; gain = 0.000
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00 . Memory (MB): peak = 683.723 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
100 Infos, 9 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
80 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 682.445 ; gain = 424.539
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 682.445 ; gain = 0.000
|
||||
synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 683.723 ; gain = 436.063
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 683.723 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Sat Apr 6 17:33:45 2019...
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Apr 10 12:50:01 2019...
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -1,8 +1,8 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Sat Apr 6 17:33:45 2019
|
||||
| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200)
|
||||
| Date : Wed Apr 10 12:50:00 2019
|
||||
| Host : WM-G75VW running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
|
||||
| Design : CPU9bits
|
||||
| Device : 7k160tifbg484-2L
|
||||
@@ -30,11 +30,11 @@ Table of Contents
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 54 | 0 | 101400 | 0.05 |
|
||||
| LUT as Logic | 54 | 0 | 101400 | 0.05 |
|
||||
| Slice LUTs* | 168 | 0 | 101400 | 0.17 |
|
||||
| LUT as Logic | 168 | 0 | 101400 | 0.17 |
|
||||
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
|
||||
| Slice Registers | 58 | 0 | 202800 | 0.03 |
|
||||
| Register as Flip Flop | 58 | 0 | 202800 | 0.03 |
|
||||
| Slice Registers | 181 | 0 | 202800 | 0.09 |
|
||||
| Register as Flip Flop | 181 | 0 | 202800 | 0.09 |
|
||||
| Register as Latch | 0 | 0 | 202800 | 0.00 |
|
||||
| F7 Muxes | 1 | 0 | 50700 | <0.01 |
|
||||
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
|
||||
@@ -57,7 +57,7 @@ Table of Contents
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 58 | Yes | Reset | - |
|
||||
| 181 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
@@ -152,17 +152,17 @@ Table of Contents
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 58 | Flop & Latch |
|
||||
| LUT4 | 23 | LUT |
|
||||
| LUT3 | 17 | LUT |
|
||||
| LUT5 | 11 | LUT |
|
||||
| FDRE | 181 | Flop & Latch |
|
||||
| LUT6 | 101 | LUT |
|
||||
| LUT5 | 42 | LUT |
|
||||
| LUT4 | 25 | LUT |
|
||||
| LUT3 | 22 | LUT |
|
||||
| OBUF | 10 | IO |
|
||||
| LUT6 | 9 | LUT |
|
||||
| LUT2 | 6 | LUT |
|
||||
| LUT2 | 9 | LUT |
|
||||
| LUT1 | 2 | LUT |
|
||||
| IBUF | 2 | IO |
|
||||
| RAMB18E1 | 1 | Block Memory |
|
||||
| MUXF7 | 1 | MuxFx |
|
||||
| LUT1 | 1 | LUT |
|
||||
| BUFG | 1 | Clock |
|
||||
+----------+------+---------------------+
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1554586396">
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1554914960">
|
||||
<File Type="PA-TCL" Name="CPU9bits.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="CPU9bits_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
|
||||
@@ -96,14 +96,6 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../Downloads/pipeline_example.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="CPU9bits"/>
|
||||
|
||||
@@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log CPU9bits_tb.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits_tb.tcl
|
||||
vivado -log CPU9bits.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
|
||||
@@ -2,11 +2,11 @@
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Sat Apr 6 17:33:19 2019
|
||||
# Process ID: 7092
|
||||
# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1
|
||||
# Start of session at: Wed Apr 10 12:49:25 2019
|
||||
# Process ID: 13540
|
||||
# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
|
||||
# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
|
||||
# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds
|
||||
# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source CPU9bits.tcl -notrace
|
||||
|
||||
Binary file not shown.
Reference in New Issue
Block a user