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It is not fully tested, but it looks pretty good
This commit is contained in:
jose.rodriguezlabra
2019-03-24 17:30:27 -04:00
parent 335280ccd5
commit efbd7b773b
6 changed files with 67 additions and 69 deletions
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41
lab2CA.srcs/sources_1/new/instructionMemory.v
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@@ -77,39 +77,38 @@ module instructionMemory(
// Binary Search
memory[0] <= 9'b000000000;
memory[0] <= 9'b000000000;
memory[1] <= 9'b000000000;
memory[2] <= 9'b000000000;
memory[3] <= 9'b000000000;
memory[4] <= 9'b000000000;
memory[5] <= 9'b000000000;
memory[6] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[5] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[6] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[7] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[8] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[9] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[10] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[11] <= 9'b011010010; //addi R2, 2 (inputAddr = 2)
memory[12] <= 9'b000111110; //lb R3, R3
memory[13] <= 9'b101011010; //banks R3, 1
memory[14] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[15] <= 9'b101000000; //loop: banks R0, 0
memory[16] <= 9'b011100010; //slt R0, R1
memory[17] <= 9'b110000001; //beq R0, Exit
memory[18] <= 9'b100100001; //j Skip0
memory[19] <= 9'b100101110; //Exit: j Loose
memory[20] <= 9'b010101000; //Skip0: add R2, R0
memory[21] <= 9'b010101010; //add R2, R1
memory[22] <= 9'b111110000; //sll R2
memory[10] <= 9'b011011010; //addi R3, 2 (inputAddr = 2)
memory[11] <= 9'b000111110; //lb R3, R3
memory[12] <= 9'b101011010; //banks R3, 1
memory[13] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[14] <= 9'b101000000; //loop: banks R0, 0
memory[15] <= 9'b011100010; //slt R0, R1
memory[16] <= 9'b110000001; //beq R0, Exit
memory[17] <= 9'b100100001; //j Skip0
memory[18] <= 9'b100101111; //Exit: j Loose
memory[19] <= 9'b101000001; //Skip0: bankl R0, 0
memory[20] <= 9'b010110000; //add R2, R0
memory[21] <= 9'b010110010; //add R2, R1
memory[22] <= 9'b111110001; //srl R2
memory[23] <= 9'b101011011; //bankl R3,1
memory[24] <= 9'b010111100; //add R3, R2
memory[25] <= 9'b101001100; //banks R1, 2
memory[26] <= 9'b000100110; //lb R0, R3
memory[27] <= 9'b010001000; //zero R1
memory[28] <= 9'b011001010; //addi R1, 1 (numAddr = 1)
memory[28] <= 9'b011001001; //addi R1, 1 (numAddr = 1)
memory[29] <= 9'b000101010; //lb R1, R1
memory[30] <= 9'b100100001; //j SkipU
memory[31] <= 9'b101110001; //j TransLoop
memory[31] <= 9'b101110010; //j TransLoop
memory[32] <= 9'b101010110; //SkipU: banks R2, 3
memory[33] <= 9'b100100001; //j SkipD
memory[34] <= 9'b100110111; //j TransLoose
@@ -122,10 +121,10 @@ module instructionMemory(
memory[41] <= 9'b010001000; //Skip1: zero R1
memory[42] <= 9'b010101100; //add R1, R2
memory[43] <= 9'b011100010; //slt R0, R1
memory[44] <= 9'b110001001; //beq R1, Go2
memory[44] <= 9'b110000001; //beq R0, Go2
memory[45] <= 9'b100100110; //j Skip2
memory[46] <= 9'b010000000; //Go2: zero R0
memory[47] <= 9'b011000010; //addi R0, 1
memory[47] <= 9'b011000001; //addi R0, 1
memory[48] <= 9'b101001111; //bankl R1,3
memory[49] <= 9'b010100010; //add R0, R1
memory[50] <= 9'b101001101; //bankl R1,2