Added back enable signals

2019-04-06 14:17:10 -04:00
parent de8740a231
commit f4b2ddebc1
1 changed files with 2 additions and 0 deletions
--- a/lab2CA.srcs/sources_1/new/CPU9bits.v
+++ b/lab2CA.srcs/sources_1/new/CPU9bits.v
@@ -28,6 +28,7 @@ module CPU9bits(
    RegFile RF(
        .clk(clk),
        .reset(reset),
+        .enable(RegEn),
        .write_index(instr[4:3]),
        .op0_idx(instr[4:3]),
        .op1_idx(instr[2:1]),
@@ -39,6 +40,7 @@ module CPU9bits(
    RegFile Bank(
        .clk(clk),
        .reset(reset),
+        .enable(bankS[1]),
        .write_index(instr[2:1]),
        .op0_idx(instr[2:1]),
        .op1_idx(2'b00),//Doesn't matter