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Fixed ALU to use the inputs we're actually going to be giving it

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WilliamMiceli
2019-02-15 16:19:42 -05:00
parent 393f7e7fc5
commit f4c923f60c
1 changed files with 4 additions and 2 deletions
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6
lab2CA.srcs/sources_1/new/ALU.v
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@@ -1,7 +1,9 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
module ALU( module ALU(
input wire [8:0] instruction, input wire [3:0] opcode,
input wire [8:0] operand0,
input wire [8:0] operand1,
output wire [8:0] result output wire [8:0] result
); );
@@ -18,7 +20,7 @@ module ALU(
// MUX chooses which result to show based on the OPCODE // MUX chooses which result to show based on the OPCODE
mux_16_1 mux_result( mux_16_1 mux_result(
.switch(instruction[8:5]), .switch(opcode),
.A(A), .A(A),
.B(B), .B(B),
.C(C), .C(C),