Collaborative - Fixes and Testbenches for Basic Modules so far

lab2CA.srcs/sources_1/new/FetchUnit.v

@@ -1,7 +1,6 @@
 `timescale 1ns / 1ps
 
 module FetchUnit(input wire clk, reset, op_idx,
-                 input wire [1:0] write_index,
                  input wire [8:0] AddrIn,
                  output wire [8:0] AddrOut);
   
@@ -11,7 +10,7 @@ module FetchUnit(input wire clk, reset, op_idx,
     register PC(
         .clk(clk),
         .reset(reset),
-        .En({write_index[0], write_index[1]}),
+        .En(2'b00),
         .Din(result_m),
         .Dout(progC_out));
     //Adds 1 to the program counter
@@ -19,11 +18,11 @@ module FetchUnit(input wire clk, reset, op_idx,
         .A(progC_out),
         .B(1'b1),
         .Cin(1'b0),
-        .Sum(result_a));
+        .Sum(AddrOut));
         
     mux_2_1 PCmux(
         .A(AddrIn),
-        .B(result_a),
+        .B(AddrOut),
         .out(result_m),
         .switch(op_idx));