jose.rodriguezlabra
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bb578e7264
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Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.runs/.jobs/vrs_config_1.xml
# lab2CA.runs/.jobs/vrs_config_2.xml
# lab2CA.srcs/sources_1/new/BasicModules.v
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2019-02-16 12:33:12 -05:00 |
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WilliamMiceli
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456fcf0804
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Few renames; added left and right shifts, possibly some other stuff
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2019-02-15 17:50:30 -05:00 |
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WilliamMiceli
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d1aa8e4ffb
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Added outputs to the MUXes for the registers
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2019-02-15 17:01:43 -05:00 |
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WilliamMiceli
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393f7e7fc5
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Added 1-bit and 9-bit OR and NOR modules
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2019-02-15 16:16:13 -05:00 |
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WilliamMiceli
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68bb7a87e8
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Framework of ALU is pretty much done
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2019-02-15 15:57:04 -05:00 |
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jose.rodriguezlabra
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0b358a6c41
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Set some comments
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2019-02-15 12:38:07 -05:00 |
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jose.rodriguezlabra
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7aa2cfff2a
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Modularized project; mux, clock, and reg done; Progress on RegFile
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2019-02-15 12:24:26 -05:00 |
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goochey
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1691adf1b5
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fetch unit
A little fetch unit
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2019-02-15 11:20:14 -05:00 |
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jose.rodriguezlabra
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b93a3779cc
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First upload
CODE HERE!!!!!!!!!!
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2019-02-08 18:18:54 -05:00 |
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