Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
# Conflicts: # lab2CA.cache/wt/webtalk_pa.xml # lab2CA.runs/.jobs/vrs_config_1.xml # lab2CA.runs/.jobs/vrs_config_2.xml # lab2CA.srcs/sources_1/new/BasicModules.v
This commit is contained in:
jose.rodriguezlabra
@@ -3,10 +3,17 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<<<<<<< HEAD
|
||||
<application name="pa" timeStamp="Fri Feb 15 12:37:44 2019">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="c2057eb1fcd843cb85f4e4ade50f1d13" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="2" type="ProjectIteration"/>
|
||||
=======
|
||||
<application name="pa" timeStamp="Fri Feb 15 17:51:37 2019">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="cabf4166fb474d5f964bb35d114df571" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
>>>>>>> 5458d273919a21255992a22a8e59ccb89544f780
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
@@ -18,6 +25,7 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddSources" value="3" type="JavaHandler"/>
|
||||
<<<<<<< HEAD
|
||||
<property name="EditDelete" value="1" type="JavaHandler"/>
|
||||
<property name="ResetLayout" value="1" type="JavaHandler"/>
|
||||
<property name="RunImplementation" value="1" type="JavaHandler"/>
|
||||
@@ -58,6 +66,61 @@ This means code written to parse this file will need to be revisited each subseq
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||||
<property name="GuiMode" value="31" type="GuiMode"/>
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||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="26" type="TclMode"/>
|
||||
=======
|
||||
<property name="CloseProject" value="1" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="1" type="JavaHandler"/>
|
||||
<property name="OpenProject" value="1" type="JavaHandler"/>
|
||||
<property name="RunSchematic" value="1" type="JavaHandler"/>
|
||||
<property name="RunSynthesis" value="3" type="JavaHandler"/>
|
||||
<property name="SetTopNode" value="5" type="JavaHandler"/>
|
||||
<property name="ShowView" value="2" type="JavaHandler"/>
|
||||
<property name="ToggleSelectAreaMode" value="1" type="JavaHandler"/>
|
||||
<property name="ToggleViewNavigator" value="4" type="JavaHandler"/>
|
||||
<property name="ViewTaskRTLAnalysis" value="2" type="JavaHandler"/>
|
||||
<property name="ViewTaskSynthesis" value="1" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="AddSrcWizard_SPECIFY_HDL_NETLIST_BLOCK_DESIGN" value="1" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="10" type="GuiHandlerData"/>
|
||||
<property name="ClosePlanner_YES" value="1" type="GuiHandlerData"/>
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||||
<property name="CmdMsgDialog_OK" value="1" type="GuiHandlerData"/>
|
||||
<property name="CreateSrcFileDialog_FILE_NAME" value="2" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="65" type="GuiHandlerData"/>
|
||||
<property name="FloatingTopDialog_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="1" type="GuiHandlerData"/>
|
||||
<property name="FloatingTopDialog_SPECIFY_NEW_TOP_MODULE" value="1" type="GuiHandlerData"/>
|
||||
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="7" type="GuiHandlerData"/>
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||||
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
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||||
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
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<property name="MainMenuMgr_PROJECT" value="1" type="GuiHandlerData"/>
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||||
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="4" type="GuiHandlerData"/>
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||||
<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_SOURCES" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_AUTO_UPDATE_HIER" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_CLOSE_PROJECT" value="1" type="GuiHandlerData"/>
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||||
<property name="PACommandNames_SELECT_AREA" value="1" type="GuiHandlerData"/>
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||||
<property name="PACommandNames_SET_AS_TOP" value="5" type="GuiHandlerData"/>
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||||
<property name="PACommandNames_TOGGLE_VIEW_NAV" value="4" type="GuiHandlerData"/>
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||||
<property name="PAViews_CODE" value="9" type="GuiHandlerData"/>
|
||||
<property name="PAViews_DEVICE" value="1" type="GuiHandlerData"/>
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||||
<property name="PAViews_SCHEMATIC" value="2" type="GuiHandlerData"/>
|
||||
<property name="PlanAheadTab_SHOW_FLOW_NAVIGATOR" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProjectDashboardView_DASHBOARD" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProjectDashboardView_TABBED_PANE" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProjectTab_RELOAD" value="4" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
|
||||
<property name="RemoveSourcesDialog_ALSO_DELETE" value="1" type="GuiHandlerData"/>
|
||||
<property name="RunGadget_SHOW_WARNING_AND_ERROR_MESSAGES_IN_MESSAGES" value="1" type="GuiHandlerData"/>
|
||||
<property name="SelectTopModuleDialog_SELECT_TOP_MODULE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_CREATE_FILE" value="2" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_HIERARCHY" value="5" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="4" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="60" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="59" type="TclMode"/>
|
||||
>>>>>>> 5458d273919a21255992a22a8e59ccb89544f780
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||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
@@ -1,6 +1,10 @@
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||||
<?xml version="1.0"?>
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||||
<Runs Version="1" Minor="0">
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<<<<<<< HEAD
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||||
<Run Id="synth_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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=======
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<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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||||
>>>>>>> 5458d273919a21255992a22a8e59ccb89544f780
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<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
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||||
</Parameters>
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||||
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||||
@@ -1,6 +1,10 @@
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||||
<?xml version="1.0"?>
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||||
<Runs Version="1" Minor="0">
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<<<<<<< HEAD
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||||
<Run Id="impl_1" LaunchDir="C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
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||||
=======
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||||
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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||||
>>>>>>> 5458d273919a21255992a22a8e59ccb89544f780
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<Parameters>
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||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
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||||
</Parameters>
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||||
|
||||
8
lab2CA.runs/.jobs/vrs_config_3.xml
Normal file
8
lab2CA.runs/.jobs/vrs_config_3.xml
Normal file
@@ -0,0 +1,8 @@
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||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
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||||
<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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||||
<Parameters>
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||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
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||||
</Parameters>
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||||
</Runs>
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||||
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||||
64
lab2CA.srcs/sources_1/new/ALU.v
Normal file
64
lab2CA.srcs/sources_1/new/ALU.v
Normal file
@@ -0,0 +1,64 @@
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`timescale 1ns / 1ps
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module ALU(
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input wire [2:0] opcode, // NOT the same as the instruction set opcode
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input wire [8:0] operand0,
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input wire [8:0] operand1,
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output wire [8:0] result
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);
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// Wires for connecting the modules to the mux
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wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H;
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// A (000) - Add
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add_9bit add0(
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.A(operand0),
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.B(operand1),
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.Cin(1'b0),
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.Sum(result_A));
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// B (001) - Subtract
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sub_9bit sub0(
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.A(operand0),
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.B(operand1),
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.C(result_B));
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// C (010) - OR
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or_9bit or0(
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.A(operand0),
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.B(operand1),
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.C(result_C));
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// D (011) - NOR
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nor_9bit nor0(
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.A(operand0),
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.B(operand1),
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.C(result_D));
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// E (100) - AND
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and_9bit and0(
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.A(operand0),
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.B(operand1),
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.Cin(1'b0),
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.Sum(result_E));
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// F (101) - Shift Logical Left
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shift_logical_left sll(
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.A(operand0),
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.B(result_F));
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// G (110) - Shift Logical Right
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shift_logical_right slr(
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.A(operand0),
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.B(result_G));
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// H (111)
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// MUX chooses which result to show based on the ALU's opcode
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mux_8_1 mux0(
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.switch(opcode),
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.A(result_A),
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.B(result_B),
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.C(result_C),
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.D(result_D),
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.E(result_E),
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.F(result_F),
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.G(result_G),
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.H(result_H),
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.out(result));
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endmodule
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@@ -1,26 +1,157 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 02/15/2019 12:18:27 PM
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||||
// Design Name:
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// Module Name: BasicModules
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// Project Name:
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||||
// Target Devices:
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||||
// Tool Versions:
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||||
// Description:
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||||
//
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||||
// Dependencies:
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||||
//
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||||
// Revision:
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||||
// Revision 0.01 - File Created
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||||
// Additional Comments:
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||||
//
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||||
//////////////////////////////////////////////////////////////////////////////////
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||||
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||||
module add_1bit(
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input wire A,
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input wire B,
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input wire Cin,
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output wire S,
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||||
output wire Cout);
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||||
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||||
assign S = (A ^ B) ^ Cin;
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assign Cout = ((A ^ B) & Cin) | (A & B);
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||||
endmodule
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module add_9bit(
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input wire [8:0] A,
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input wire [8:0] B,
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input wire Cin,
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output wire [8:0] Sum,
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||||
output wire Cout);
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||||
|
||||
wire C_add0;
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wire C_add1;
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wire C_add2;
|
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wire C_add3;
|
||||
wire C_add4;
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wire C_add5;
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||||
wire C_add6;
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||||
wire C_add7;
|
||||
|
||||
add_1bit add0(
|
||||
.A(A[0]),
|
||||
.B(B[0]),
|
||||
.Cin(Cin),
|
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.S(Sum[0]),
|
||||
.Cout(C_add0));
|
||||
|
||||
add_1bit add1(
|
||||
.A(A[1]),
|
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.B(B[1]),
|
||||
.Cin(C_add0),
|
||||
.S(Sum[1]),
|
||||
.Cout(C_add1));
|
||||
|
||||
add_1bit add2(
|
||||
.A(A[2]),
|
||||
.B(B[2]),
|
||||
.Cin(C_add1),
|
||||
.S(Sum[2]),
|
||||
.Cout(C_add2));
|
||||
|
||||
add_1bit add3(
|
||||
.A(A[3]),
|
||||
.B(B[3]),
|
||||
.Cin(C_add2),
|
||||
.S(Sum[3]),
|
||||
.Cout(C_add3));
|
||||
|
||||
add_1bit add4(
|
||||
.A(A[4]),
|
||||
.B(B[4]),
|
||||
.Cin(C_add3),
|
||||
.S(Sum[4]),
|
||||
.Cout(C_add4));
|
||||
|
||||
add_1bit add5(
|
||||
.A(A[5]),
|
||||
.B(B[5]),
|
||||
.Cin(C_add4),
|
||||
.S(Sum[5]),
|
||||
.Cout(C_add5));
|
||||
|
||||
add_1bit add6(
|
||||
.A(A[6]),
|
||||
.B(B[6]),
|
||||
.Cin(C_add5),
|
||||
.S(Sum[6]),
|
||||
.Cout(C_add6));
|
||||
|
||||
add_1bit add7(
|
||||
.A(A[7]),
|
||||
.B(B[7]),
|
||||
.Cin(C_add6),
|
||||
.S(Sum[7]),
|
||||
.Cout(C_add7));
|
||||
|
||||
add_1bit add8(
|
||||
.A(A[8]),
|
||||
.B(B[8]),
|
||||
.Cin(C_add7),
|
||||
.S(Sum[8]),
|
||||
.Cout(Cout));
|
||||
|
||||
endmodule
|
||||
|
||||
module and_1bit(
|
||||
input wire A,
|
||||
input wire B,
|
||||
output wire C);
|
||||
|
||||
assign C = A & B;
|
||||
|
||||
endmodule
|
||||
|
||||
module and_9bit(
|
||||
input wire [8:0] A,
|
||||
input wire [8:0] B,
|
||||
output wire [8:0] C);
|
||||
|
||||
and_1bit and0(
|
||||
.A(A[0]),
|
||||
.B(B[0]),
|
||||
.C(C[0]));
|
||||
|
||||
and_1bit and1(
|
||||
.A(A[1]),
|
||||
.B(B[1]),
|
||||
.C(C[1]));
|
||||
|
||||
and_1bit and2(
|
||||
.A(A[2]),
|
||||
.B(B[2]),
|
||||
.C(C[2]));
|
||||
|
||||
and_1bit and3(
|
||||
.A(A[3]),
|
||||
.B(B[3]),
|
||||
.C(C[3]));
|
||||
|
||||
and_1bit and4(
|
||||
.A(A[4]),
|
||||
.B(B[4]),
|
||||
.C(C[4]));
|
||||
|
||||
and_1bit and5(
|
||||
.A(A[5]),
|
||||
.B(B[5]),
|
||||
.C(C[5]));
|
||||
|
||||
and_1bit and6(
|
||||
.A(A[6]),
|
||||
.B(B[6]),
|
||||
.C(C[6]));
|
||||
|
||||
and_1bit and7(
|
||||
.A(A[7]),
|
||||
.B(B[7]),
|
||||
.C(C[7]));
|
||||
|
||||
and_1bit and8(
|
||||
.A(A[8]),
|
||||
.B(B[8]),
|
||||
.C(C[8]));
|
||||
|
||||
module BasicModules();
|
||||
endmodule
|
||||
|
||||
module gen_clock();
|
||||
@@ -33,7 +164,248 @@ module gen_clock();
|
||||
end
|
||||
endmodule
|
||||
|
||||
<<<<<<< HEAD
|
||||
//To enable register, input 00 to En, register is always outputting contents
|
||||
=======
|
||||
module mux_4_1(input wire [1:0] switch,
|
||||
input wire [8:0] A,B,C,D,
|
||||
output reg [8:0] out);
|
||||
|
||||
always @(A,B,C,D,switch) begin
|
||||
case (switch)
|
||||
2'b00 : out = A;
|
||||
2'b01 : out = B;
|
||||
2'b10 : out = C;
|
||||
2'b11 : out = D;
|
||||
default : out = 9'bxxxxxxxxx;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module mux_8_1(
|
||||
input wire [2:0] switch,
|
||||
input wire [8:0] A,B,C,D,E,F,G,H,
|
||||
output reg [8:0] out);
|
||||
|
||||
always @(A,B,C,D,E,F,G,H,switch) begin
|
||||
case (switch)
|
||||
3'b000 : out = A;
|
||||
3'b001 : out = B;
|
||||
3'b010 : out = C;
|
||||
3'b011 : out = D;
|
||||
3'b100 : out = E;
|
||||
3'b101 : out = F;
|
||||
3'b110 : out = G;
|
||||
3'b111 : out = H;
|
||||
default : out = 9'bxxxxxxxxx;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module mux_16_1(
|
||||
input wire [3:0] switch,
|
||||
input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,
|
||||
output reg [8:0] out);
|
||||
|
||||
always @(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,switch) begin
|
||||
case (switch)
|
||||
4'b0000 : out = A;
|
||||
4'b0001 : out = B;
|
||||
4'b0010 : out = C;
|
||||
4'b0011 : out = D;
|
||||
4'b0100 : out = E;
|
||||
4'b0101 : out = F;
|
||||
4'b0110 : out = G;
|
||||
4'b0111 : out = H;
|
||||
4'b1000 : out = I;
|
||||
4'b1001 : out = J;
|
||||
4'b1010 : out = K;
|
||||
4'b1011 : out = L;
|
||||
4'b1100 : out = M;
|
||||
4'b1101 : out = N;
|
||||
4'b1110 : out = O;
|
||||
4'b1111 : out = P;
|
||||
default : out = 9'bxxxxxxxxx;
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module nor_1bit(
|
||||
input wire A,
|
||||
input wire B,
|
||||
output wire C);
|
||||
|
||||
assign C = A |~ B;
|
||||
|
||||
endmodule
|
||||
|
||||
module nor_9bit(
|
||||
input wire [8:0] A,
|
||||
input wire [8:0] B,
|
||||
output wire [8:0] C);
|
||||
|
||||
nor_1bit nor0(
|
||||
.A(A[0]),
|
||||
.B(B[0]),
|
||||
.C(C[0]));
|
||||
|
||||
nor_1bit nor1(
|
||||
.A(A[1]),
|
||||
.B(B[1]),
|
||||
.C(C[1]));
|
||||
|
||||
nor_1bit nor2(
|
||||
.A(A[2]),
|
||||
.B(B[2]),
|
||||
.C(C[2]));
|
||||
|
||||
nor_1bit nor3(
|
||||
.A(A[3]),
|
||||
.B(B[3]),
|
||||
.C(C[3]));
|
||||
|
||||
nor_1bit nor4(
|
||||
.A(A[4]),
|
||||
.B(B[4]),
|
||||
.C(C[4]));
|
||||
|
||||
nor_1bit nor5(
|
||||
.A(A[5]),
|
||||
.B(B[5]),
|
||||
.C(C[5]));
|
||||
|
||||
nor_1bit nor6(
|
||||
.A(A[6]),
|
||||
.B(B[6]),
|
||||
.C(C[6]));
|
||||
|
||||
nor_1bit nor7(
|
||||
.A(A[7]),
|
||||
.B(B[7]),
|
||||
.C(C[7]));
|
||||
|
||||
nor_1bit nor8(
|
||||
.A(A[8]),
|
||||
.B(B[8]),
|
||||
.C(C[8]));
|
||||
|
||||
endmodule
|
||||
|
||||
module not_1bit(
|
||||
input wire A,
|
||||
output wire B);
|
||||
|
||||
assign B = ~A;
|
||||
|
||||
endmodule
|
||||
|
||||
module not_9bit(
|
||||
input wire [8:0] A,
|
||||
output wire [8:0] B);
|
||||
|
||||
not_1bit not0(
|
||||
.A(A[0]),
|
||||
.B(B[0]));
|
||||
|
||||
not_1bit not1(
|
||||
.A(A[1]),
|
||||
.B(B[1]));
|
||||
|
||||
not_1bit not2(
|
||||
.A(A[2]),
|
||||
.B(B[2]));
|
||||
|
||||
not_1bit not3(
|
||||
.A(A[3]),
|
||||
.B(B[3]));
|
||||
|
||||
not_1bit not4(
|
||||
.A(A[4]),
|
||||
.B(B[4]));
|
||||
|
||||
not_1bit not5(
|
||||
.A(A[5]),
|
||||
.B(B[5]));
|
||||
|
||||
not_1bit not6(
|
||||
.A(A[6]),
|
||||
.B(B[6]));
|
||||
|
||||
not_1bit not7(
|
||||
.A(A[7]),
|
||||
.B(B[7]));
|
||||
|
||||
not_1bit not8(
|
||||
.A(A[8]),
|
||||
.B(B[8]));
|
||||
|
||||
endmodule
|
||||
|
||||
module or_1bit(
|
||||
input wire A,
|
||||
input wire B,
|
||||
output wire C);
|
||||
|
||||
assign C = A | B;
|
||||
|
||||
endmodule
|
||||
|
||||
module or_9bit(
|
||||
input wire [8:0] A,
|
||||
input wire [8:0] B,
|
||||
output wire [8:0] C);
|
||||
|
||||
or_1bit or0(
|
||||
.A(A[0]),
|
||||
.B(B[0]),
|
||||
.C(C[0]));
|
||||
|
||||
or_1bit or1(
|
||||
.A(A[1]),
|
||||
.B(B[1]),
|
||||
.C(C[1]));
|
||||
|
||||
or_1bit or2(
|
||||
.A(A[2]),
|
||||
.B(B[2]),
|
||||
.C(C[2]));
|
||||
|
||||
or_1bit or3(
|
||||
.A(A[3]),
|
||||
.B(B[3]),
|
||||
.C(C[3]));
|
||||
|
||||
or_1bit or4(
|
||||
.A(A[4]),
|
||||
.B(B[4]),
|
||||
.C(C[4]));
|
||||
|
||||
or_1bit or5(
|
||||
.A(A[5]),
|
||||
.B(B[5]),
|
||||
.C(C[5]));
|
||||
|
||||
or_1bit or6(
|
||||
.A(A[6]),
|
||||
.B(B[6]),
|
||||
.C(C[6]));
|
||||
|
||||
or_1bit or7(
|
||||
.A(A[7]),
|
||||
.B(B[7]),
|
||||
.C(C[7]));
|
||||
|
||||
or_1bit or8(
|
||||
.A(A[8]),
|
||||
.B(B[8]),
|
||||
.C(C[8]));
|
||||
|
||||
endmodule
|
||||
|
||||
>>>>>>> 5458d273919a21255992a22a8e59ccb89544f780
|
||||
module register(input wire clk, reset,
|
||||
input wire [1:0] En,
|
||||
input wire [8:0] Din,
|
||||
@@ -53,6 +425,7 @@ module register(input wire clk, reset,
|
||||
|
||||
endmodule
|
||||
|
||||
<<<<<<< HEAD
|
||||
//Mux follows intuitive switching
|
||||
module mux(input wire [1:0] switch,
|
||||
input wire [8:0] A,B,C,D,
|
||||
@@ -75,6 +448,57 @@ module mux(input wire [1:0] switch,
|
||||
out = "ZZZZZZZZZ";
|
||||
end
|
||||
end
|
||||
=======
|
||||
module shift_logical_left(
|
||||
input wire [8:0] A,
|
||||
output wire [8:0] B);
|
||||
|
||||
assign B = {A[7:0],A[8]};
|
||||
>>>>>>> 5458d273919a21255992a22a8e59ccb89544f780
|
||||
|
||||
endmodule
|
||||
|
||||
module shift_logical_right(
|
||||
input wire [8:0] A,
|
||||
output wire [8:0] B);
|
||||
|
||||
assign B = {A[0],A[8:1]};
|
||||
|
||||
endmodule
|
||||
|
||||
module sub_9bit(
|
||||
input wire [8:0] A,
|
||||
input wire [8:0] B,
|
||||
output wire [8:0] C);
|
||||
|
||||
wire [8:0] D;
|
||||
|
||||
twos_compliment_9bit two_comp0(
|
||||
.A(B),
|
||||
.C(D));
|
||||
|
||||
add_9bit add0(
|
||||
.A(A),
|
||||
.B(D),
|
||||
.Cin(1'b0),
|
||||
.Sum(C));
|
||||
|
||||
endmodule
|
||||
|
||||
module twos_compliment_9bit(
|
||||
input wire [8:0] A,
|
||||
output wire [8:0] B);
|
||||
|
||||
wire [8:0] C;
|
||||
|
||||
not_9bit not0(
|
||||
.A(A),
|
||||
.B(C));
|
||||
|
||||
add_9bit add0(
|
||||
.A(C),
|
||||
.B(9'b000000000),
|
||||
.Cin(1'b1),
|
||||
.Sum(B));
|
||||
|
||||
endmodule
|
||||
@@ -1,24 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 02/15/2019 12:21:16 PM
|
||||
// Design Name:
|
||||
// Module Name: RegFile
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module RegFile(input wire clk, reset,
|
||||
input wire [1:0] write_index, op0_idx, op1_idx,
|
||||
@@ -57,18 +37,20 @@ module RegFile(input wire clk, reset,
|
||||
.Din(write_data),
|
||||
.Dout(r3_out));
|
||||
|
||||
mux m0(
|
||||
mux_4_1 m0(
|
||||
.A(r0_out),
|
||||
.B(r1_out),
|
||||
.C(r2_out),
|
||||
.D(r3_out),
|
||||
.out(op0),
|
||||
.switch(op0_idx));
|
||||
|
||||
mux m1(
|
||||
mux_4_1 m1(
|
||||
.A(r0_out),
|
||||
.B(r1_out),
|
||||
.C(r2_out),
|
||||
.D(r3_out),
|
||||
.out(op1),
|
||||
.switch(op1_idx));
|
||||
|
||||
endmodule
|
||||
|
||||
17
lab2CA.xpr
17
lab2CA.xpr
@@ -3,7 +3,7 @@
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="39" Path="C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr">
|
||||
<Project Version="7" Minor="39" Path="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="0a5803efda44405bb28bbf43ba22e808"/>
|
||||
@@ -66,8 +66,16 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -83,8 +91,7 @@
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="RegFile"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TopModule" Val="ALU"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
@@ -97,9 +104,7 @@
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="RegFile"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TopModule" Val="ALU"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SimMode" Val="post-implementation"/>
|
||||
|
||||
Reference in New Issue
Block a user