9 Commits

Author	SHA1	Message	Date
jose.rodriguezlabra	026eb65861	Fixed bugs, finished BEQ, Added Halt	2019-03-13 11:14:52 -04:00
jose.rodriguezlabra	172238b4e0	Created CPU9bits file	2019-03-10 13:42:30 -04:00
goochey	c047c801aa	Lots of changes ... Added a decoder and implemented it into the regFile. We probably want to change the testbench so that there arent many changes in one clock cycle. Altered the register file so that it only has the one bit enable decided by the decoder and updated the regFile and fetchUnit to reflect this. Went over the fetch unit with Martin, he said it is okay.	2019-02-27 12:06:17 -05:00
WilliamMiceli	1734d58b47	Adjusted indentation of testbench code	2019-02-25 13:27:22 -05:00
goochey	6550b48599	fetch unit test	2019-02-20 11:31:25 -05:00
goochey	54cccd419f	Lots ... Lots	2019-02-16 17:40:18 -05:00
WilliamMiceli	d1aa8e4ffb	Added outputs to the MUXes for the registers	2019-02-15 17:01:43 -05:00
WilliamMiceli	337bf5cf13	Removed comment blocks	2019-02-15 14:34:59 -05:00
jose.rodriguezlabra	7aa2cfff2a	Modularized project; mux, clock, and reg done; Progress on RegFile	2019-02-15 12:24:26 -05:00