3f01492398
There is a testbench but when I try to run it on my computer it brings up some regFile simulation even though SLT is set to top. Not sure if its my pc or the code
11 lines
198 B
Plaintext
11 lines
198 B
Plaintext
{
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"design": {
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"design_info": {
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"boundary_crc": "0x0",
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"name": "design_1",
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"synth_flow_mode": "Hierarchical",
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"tool_version": "2018.3"
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},
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"design_tree": {}
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}
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} |