165 lines
3.0 KiB
Verilog
165 lines
3.0 KiB
Verilog
`timescale 1ns / 1ps
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module CPU9bits(
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input wire reset, clk,
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output wire [8:0] result,
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output wire done
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);
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wire [8:0] RFIn,FUAddr, op0_ext, op1_ext, wr_ext, op0_sub, op1_sub, op0_zero, op1_zero, op0_and, op1_and, newOp0, newOp1;
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wire [1:0] instr, op0_idx, op1_idx;
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wire fetchBranch, RegEn, compare0, compare1;
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wire [50:0] EMIn;
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wire [52:0] FDOut,FDPipOut;
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wire [61:0] EMOut, EMPipOut;
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assign result = RFIn;
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assign EMIn = {FDPipOut[50:42], newOp0, newOp1, FDPipOut[23:0]};
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FDModule FD(
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.reset(reset),
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.clk(clk),
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.FUIdx(fetchBranch),
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.En(RegEn),
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.RFIn(RFIn),
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.AddrIn(FUAddr),
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.RFIdx(instr),
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.result(FDOut), ////////////////////
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.done(done)
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//.compare0(compare0),
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//.compare1(compare1),
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//.op0_idx(op0_idx),
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//.op1_idx(op1_idx)
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);
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fDPipReg pipe1(
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.clk(clk),
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.reset(reset),
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.En(1'b0),
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.Din(FDOut), ///////////////////
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.Dout(FDPipOut)///////////////////
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);
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EMModule EM(
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.reset(reset),
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.clk(clk),
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.PipIn(EMIn),/////////////////
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.PipOut(EMOut)
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);
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eMPipReg pipe2(
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.clk(clk),
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.reset(reset),
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.En(1'b0),
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.Din(EMOut),
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.Dout(EMPipOut)
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);
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WMUdule W(
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.PipIn(EMPipOut),
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.RFIn(RFIn),
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.FUAddr(FUAddr),
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.instr(instr),
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.fetchBranch(fetchBranch),
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.RegEn(RegEn)
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);
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sign_extend_2bit ext0(
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.A(FDPipOut[46:45]),
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.B(op0_ext)
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);
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sign_extend_2bit ext1(
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.A(FDPipOut[44:43]),
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.B(op1_ext)
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);
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sign_extend_2bit ext2(
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.A(instr),
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.B(wr_ext)
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);
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sub_9bit sub0(
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.A(op0_ext),
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.B(wr_ext),
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.C(op0_sub)
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);
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sub_9bit sub1(
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.A(op1_ext),
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.B(wr_ext),
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.C(op1_sub)
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);
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BEQ beq0(
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.A(op0_sub),
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.B(op0_zero)
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);
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BEQ beq1(
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.A(op1_sub),
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.B(op1_zero)
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);
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and_9bit and0(
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.A(~op0_zero),
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.B({8'b00000000,FDPipOut[52]}),
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.C(op0_and)
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);
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and_9bit and1(
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.A(~op1_zero),
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.B({8'b00000000,FDPipOut[51]}),
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.C(op1_and)
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);
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mux_2_1 mux0(
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.switch(op0_and[0]),
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//.switch(1'b0),
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.A(FDPipOut[41:33]),
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.B(EMPipOut[33:25]), //ALUOut
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.out(newOp0)
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);
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mux_2_1 mux1(
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.switch(op1_and[0]),
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//.switch(1'b0),
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.A(FDPipOut[32:24]),
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.B(EMPipOut[33:25]), //ALUOut
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.out(newOp1)
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);
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endmodule
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module CPU9bits_tb();
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reg clk, reset;
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wire done;
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wire [8:0] result;
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initial begin
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clk = 1'b0;
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end
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always begin
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#5 clk = ~clk; // Period to be determined
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end
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CPU9bits CPU9bits0(
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.reset(reset),
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.clk(clk),
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.done(done),
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.result(result));
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initial begin
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#5
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reset = 1'b1;
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#10
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reset = 1'b0;
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#200
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$finish;
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end
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endmodule
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