jose.rodriguezlabra
ddf47c7eee
Tweaked forwarding check. Program 3 works with a few stalls
2019-04-12 00:01:27 -04:00
Johannes
a3064a836b
Nonsense
2019-04-11 19:23:15 -04:00
Johannes
bc9c02322c
Added forwarding
2019-04-11 18:36:00 -04:00
jose.rodriguezlabra
42d2bf2d80
Fixed pip enables, fixed Nop/Halt
2019-04-11 17:32:17 -04:00
WilliamMiceli
b1f1a7339b
Minor adjustments
2019-04-10 12:52:42 -04:00
Johannes
e6cb8e536b
Added Pipeline
2019-04-06 17:51:44 -04:00
WilliamMiceli
443d01eba1
Modified sensitivities for result; Vivado metadata
2019-03-30 15:59:43 -04:00
WilliamMiceli
ea0111542a
Result output of CPU pretty much implemented; not yet tested
2019-03-29 18:16:45 -04:00
WilliamMiceli
acf7f9e92b
Registers and Banks don't need an enable, should be ignored using MUXes
2019-03-29 18:10:13 -04:00
WilliamMiceli
2479eefa00
Formatted things to look a little nicer
2019-03-29 17:23:26 -04:00
WilliamMiceli
445f5ce830
Removed CLK, as it is not needed
2019-03-29 16:16:36 -04:00
WilliamMiceli
5353c8c22e
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
...
# Conflicts:
# lab2CA.cache/wt/webtalk_pa.xml
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
# lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
# lab2CA.srcs/sources_1/new/CPU9bits.v
# lab2CA.srcs/sources_1/new/dataMemory.v
2019-03-24 19:31:28 -04:00
WilliamMiceli
7490815502
Making fixes to Bubble Sort
2019-03-24 19:27:59 -04:00
Johannes
be06f4e457
Just changes made for simulations
2019-03-24 18:55:49 -04:00
Johannes
03df69372a
String Compare Working
2019-03-24 17:05:09 -04:00
Johannes
e8ada91e08
BEQ and LD fix
2019-03-24 16:05:16 -04:00
jose.rodriguezlabra
94f0267a13
stuff
2019-03-24 14:16:03 -04:00
jose.rodriguezlabra
bab680ea27
Added bank to CPU9bits
2019-03-24 12:11:12 -04:00
Johannes
c85ad153dc
Tested the instructions using the instruction memory
...
All of the instructions seem to be working other than beq. I might just be calling it wrong
2019-03-20 12:08:24 -04:00
Johannes
0f55e62a2e
Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2
2019-03-16 14:56:00 -04:00
Johannes
e8554a5a9a
Minor changes to CPU
2019-03-16 14:55:37 -04:00
jose.rodriguezlabra
eeb9c7c318
Tested zero
2019-03-16 14:55:11 -04:00
Johannes
fa5caec5dd
Added memories to the CPU
2019-03-16 14:37:46 -04:00
jose.rodriguezlabra
dfd8753a62
Implemented SEs
2019-03-16 14:09:53 -04:00
jose.rodriguezlabra
5cbe490aae
Added link instruction
2019-03-16 14:01:32 -04:00
WilliamMiceli
934c73e899
Small formatting change
2019-03-16 13:44:44 -04:00
jose.rodriguezlabra
08e3659ba3
Better Sim
2019-03-14 14:37:58 -04:00
jose.rodriguezlabra
11a1d99e92
Computer works (kinda)
2019-03-13 12:51:44 -04:00
jose.rodriguezlabra
026eb65861
Fixed bugs, finished BEQ, Added Halt
2019-03-13 11:14:52 -04:00
Johannes
cb91f6656a
Many Changes
...
I added a comparator, I updated the control unit so that it now uses the 4 bit ALU opcode instead of the 3 bit from before. I added testbenches to the control unit and the slt and comparator modules. However, like before I unable to run the simulation on my desktop. Finally, i added the program code for the equation solver as a test bench in the CPU9bit module
2019-03-12 21:14:27 -04:00
Johannes
460fc3e4ed
CPU
...
LOTS
2019-03-10 16:32:25 -04:00
jose.rodriguezlabra
7406cddb64
case for control unit
2019-03-10 14:05:21 -04:00
jose.rodriguezlabra
172238b4e0
Created CPU9bits file
2019-03-10 13:42:30 -04:00
