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047efb7f1fcedce631296346d818627cfb6d734a
WMU-ECE-3570-Lab/lab2CA.sim/sim_1/behav/xsim
History
Johannes cb91f6656a Many Changes 
I added a comparator, I updated the control unit so that it now uses the 4 bit ALU opcode instead of the 3 bit from before. I added testbenches to the control unit and the slt and comparator modules. However, like before I unable to run the simulation on my desktop. Finally, i added the program code for the equation solver as a test bench in the CPU9bit module
2019-03-12 21:14:27 -04:00
..
xsim.dir
Many Changes
2019-03-12 21:14:27 -04:00
add1bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
add1bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
add9bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
add9bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
alu_tb_vlog.prj
Lots
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alu_tb.tcl
Lots
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ALU_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
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ALU.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
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and1bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
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and1bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
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and9bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
and9bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
comparator_tb_vlog.prj
Many Changes
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comparator_tb.tcl
Many Changes
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decoder_tb_vlog.prj
Lots of changes
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decoder_tb.tcl
Lots of changes
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fetchUnit_tb_vlog.prj
fetch unit test
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fetchUnit_tb.tcl
fetch unit test
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glbl.v
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
mux_2_1_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
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mux_2_1_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
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mux_4_1_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
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mux_4_1_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
mux_8_1_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
mux_8_1_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
nor_1bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
nor_1bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
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nor_9bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
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nor_9bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
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not_1bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
not_1bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
not_9bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
not_9bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
or_1bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
or_1bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
or_9bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
or_9bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
regFile_tb_vlog.prj
Lots
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regFile_tb.tcl
Lots
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register_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
register_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
shift_logical_left_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
shift_logical_left_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
shift_logical_right_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
shift_logical_right_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
slt_tb_vlog.prj
Added SLT
2019-03-12 19:49:46 -04:00
slt_tb.tcl
Added SLT
2019-03-12 19:49:46 -04:00
sub_9bit_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
sub_9bit_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
twos_compliment_tb_vlog.prj
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
twos_compliment_tb.tcl
Collaborative - Fixes and Testbenches for Basic Modules so far
2019-02-16 16:29:12 -05:00
webtalk_4236.backup.jou
Added SLT
2019-03-12 19:49:46 -04:00
webtalk_5116.backup.jou
Many Changes
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webtalk_6512.backup.jou
Many Changes
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webtalk_7548.backup.jou
Many Changes
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webtalk_18368.backup.jou
Many Changes
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webtalk.jou
Many Changes
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xelab.pb
Many Changes
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xvlog.pb
Many Changes
2019-03-12 21:14:27 -04:00