352aeefd1b640bbf589588a3b53f9239356b2cbb
ECE 3570 Lab
Things to fix
- Make RAM write edge-triggered only
- RTL_RAM is what it needs to be showing as, since VIvado will recognize it as such
- Make ROM asyncronous (can be read at any time)
- RTL_ROM is what it needs to be showing as, since VIvado will recognize it as such
- Get rid of if statememnts in RAM and ROM
- Get programs working properly
Description
Languages
C
33.3%
Verilog
26.9%
PureBasic
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Tcl
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